JPS62109458A - Repeater - Google Patents

Abstract

PURPOSE:To minimize the repeating delay time and to avoid a discontinuous preamble by switching the transmission output to the data signal read out of the output of a preamble generator after obtaining the coincidence between the read-out data signal and the output of the preamble generator. CONSTITUTION:A control circuit 6 inputs a trasmission enable signal 106, a transmission data signal 111, a preamble signal 112 and a transmission clock signal 108 and outputs control signals 107 and 113. An AND gate 7 inputs the signals 107 and 108 and outputs a reading clock signal 109. A preamble generator 8 inputs the signal 108 and outputs the signal 112. Then a selector 9 inputs the signals 111, 112, and 113 and outputs a signal 114 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a repeater, and particularly to a repeater used in a local area network for all data communications.

[Conventional technology]

Local area network repeaters must transmit and receive all burst data signals with a preamble asynchronously, so they use input n first-out buffers (hereinafter referred to as FI).
(abbreviated as FO).

In the first conventional example of such a repeater, when a data signal arrives, the data signal is sequentially written into a FIFO using its clock (receiving clock), and the data signal is determined by the difference between the receiving clock and the transmitting clock for relaying and the maximum data length. At the time when the number of data has been written, all reading is started using the transmission clock to obtain a data signal to be transmitted.

Therefore, the first conventional example has the disadvantage that a considerable amount of time is required from the arrival of the data signal to the start of transmission.

In a second conventional example that solves this drawback, two preambles of the required data are written in advance, and as soon as all arrivals of data signals are detected, reading of the stored preambles is started.

A read '''-λ has been proposed in which the readout is followed by the readout of the data signal arriving at fi1 [7±. can.

[Problems to be Solved by the Invention] The probability of data errors occurring is high for a while after the reception of data signals begins. For this reason, in the second conventional example, there is a risk that the preamble may become discontinuous when transitioning from reading the pre-written preamble to reading the arrived data signal (the beginning part of which is also the preamble). There is a drawback that there is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a repeater which can solve the above-mentioned drawbacks, minimize the total relay delay time, and prevent the preamble from becoming discontinuous.

[Means for solving problems]

In the repeater of the present invention, in a repeater that relays the data signal by reading it with a write clock having a preamble and a read clock that is not synchronized, all the signals having the same pattern as the preamble are read out. When the preamble generating means generated by the jH cyclovuku and the control signal are input, the first input is 2, the first out 1.
A selection means for outputting the read output of the buffer by selecting all of the outputs and outputting all of the outputs when the input is not input, and a selection means for selecting and outputting all of the outputs when the readout output of the buffer is not input; transmission control means for detecting the completion of reading of the first-in first-out buffer and stopping the transmission, and determining whether the read output of the first-in first-out buffer and the output of the preamble generating means match each other after a predetermined time after the start of retrieval of the first-in first-out buffer. If they match, the control signal is outputted until the output of the first-in, first-out buffer is completed, and if they do not match, the control means stops all of the seven reading clocks by a predetermined number of pulses and then checks the match again. It consists of:

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to one drawing.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The repeater shown in FIG. 1 receives a data signal 101'z and a receive enable signal 102'z. Write black/T signal 10
3. A receiving circuit 1 (for example, AMD's Am7992) outputs a received data signal 104'i, and a receiving enable signal 102'i. The received data signal 104 is connected to the data input terminal DI,
, DI, and the write clock signal 103 . The read clock signal 10'lr is input to the clock input terminals ICL and OCL, and the signal 110° and the transmission data signal 111 are output from the data output terminals Do, DO1.
748225) of Company I, and the reception enable signal 102.
A synchronization circuit 3 inputs the transmit clock 715 and outputs a signal 105t-, an OR gate 4 inputs the signals 105, 1'lOf, and outputs a transmit enable pull signal 106, and a transmit enable signal 106. Input signal 114 and transmit clock signal 108 . A transmitting circuit 5 (for example, AMD's Am7992) outputting a data signal 115 and a transmitting enable signal 106 . Transmission day/evening signal 111, preamble signal 112. A control circuit 6 receives all transmission clock signals 108 and outputs control signals 107, 113ffi, and control signals 107. An AND game that inputs the transmission clock signal 108 and outputs the read clock signal 109, a preamble generator 8 that inputs the transmission clock signal 108 and outputs the preamble signal 112, and a transmission data signal 11.
1° pre-apple signal 112. The control signal 113t is configured to include a selector 9 which outputs a control signal 113t and a human input signal 114.

FIG. 2 is a time chart for explaining the entire operation of the embodiment shown in FIG.

The operation of the repeater shown in FIG. 1 will be explained with reference to FIG. 2.

A data signal 1.01 is input to the receiving circuit 1 from time t1 to time t6. As shown in FIG. 2, the data signal 101 has a preamble portion hatched with diagonal lines and a data portion outlined in white. It is assumed that the bit pattern of the preamble portion is a repetition of @1'' and 'O''.

The receiving circuit l receives the data signal 101 while the data signal 101 is being input.
, 'e is detected and outputs '1' as the reception enable signal 102 from time t1 to time t1.

Ma7?1. % The clock of the data signal 101 is completely recovered from the preamble portion, and when the recovered clock becomes stable, it is output as the write clock signal 103 and simultaneously output as the received data signal 104. Until the clock reproduction becomes stable, the corresponding (head) part of the data signal 101 does not become the received data signal 104 and is discarded.

The FIF02 receives a receive enable signal 102 . Write received data signal 104 gold.

Immediately after the reception enable signal 102 rises, the synchronization circuit 3 generates a signal 105 in synchronization with the transmission clock signal 10H.
Immediately after the fall of the reception enable signal 102, the signal Therefore, in Figure 2, from 1 hour Jts to 1 hour
The signal 105 is shown to be "1" up to n.

When No. 1g No. 105 rises, the transmission enable signal 106, which is the output of OR gate 4, becomes 1'' (PIF (Since the mining of J2 has not started yet, the signal 110 is +v Os
).

The control circuit 6 learns time t from the rising edge of the transmission enable signal 106. Thereafter, the reception enable signal 102. written to FIFO2. The first bit of the received data signal 104 is the data output terminal DO.

Time to reach DOl and committed clock signal 1
03 and the transmission clock signal 108 and the maximum data length of the data signal 101, the interest is counted for n and 4 hours, and at time t3 when these times have elapsed, the control signal 107 is 11" full output.

The transmitting circuit 5 always outputs the transmitting clock signal 108, and the AND circuit 7 outputs the transmitting clock signal 1ost-h as the clock signal 109 when the control signal 107 rises. As a result, FIFO2 is.

Included receive enable signal 102. The received data signal 104 is converted to signal 1 by the read clock signal 109.
10. It is read out as a transmission data signal 111. - The preamble generator 8 always outputs the next preamble signal 112 in synchronization with the transmission clock signal 108. The bit pattern of the preamble signal 112 is the transmission data signal 11.
The bit pattern is the same as that of the preamble part of No.1.

The control circuit 6 performs a match determination between the transmission data signal 111 and the preamble signal 112 at time t4 after counting the total for a certain period of time from time t3, and if they match, the control circuit 6 outputs the control signal 11.
``1'' is output as 3.

If they do not match, the transmission clock signal 108 is controlled by one clock cycle of the transmission clock signal 107't"t"t"0", and the reading of the transmission data signal 111 is paused for this period, and then the transmission data signal 111 is stopped for this period, and then the transmission data signal 111 is read at 1 time 1. The nine times the match is complete. Since the bit pattern of the preamble is a repetition of 11'' and IIO'', if there is a mismatch at time t4, there will always be a match at time ts. Therefore, the control signal 113 rises at time t4 or t5. Note that the reason why the coincidence determination is not performed at time t3 but is waited until time t4 is to wait until the probability of data error occurrence in the transmitted data signal 111 becomes sufficiently small. 7? :1 Time count from time t3 to time t4.

The time mentioned earlier 1. A transmission clock signal 108 is input to the control circuit 6 in order to count the time from t3 to time t3.

The selector 9 is controlled to selectively output the preamble signal 112 when the control signal 113 is 1O'', and selectively output the transmission data signal 111f when the control signal 113 is ``1''.
The signal 114 is switched from the preamble signal 112 (the cross-hatched portion in Figure 2) to the transmission data signal 111 at the same time as the control signal 113 rises. Moreover, since it has been confirmed that the two signals before switching match, the preamble portion of signal 114 (the cross-hatched portion and the diagonally hatched portion in FIG. 2) will not become discontinuous during this switching. .

The transmission circuit 5 relays the signal 114e and outputs it as the t data signal 115 while the transmission enable signal 106 is 11'', so the transmission of the data signal 115 starts from time t3.At time t8, the signal 11o is transmitted.

Reading of the transmission data signal 111 is completed, and the signal 110 becomes 'O'. Since the signal 105 was 'O' at time t7 before this time, the transmission enable signal 106 becomes 'O' at time ts. Then, the output of the data signal 115 is stopped. When the enable signal 106 falls, the control circuit 6 detects the time ta't' and the control signals 107, 113i''.
0'''. As a result, the output of the read clock signal 109 is stopped, and the selector 9 outputs the preamble signal 112 as the signal 114, and the embodiment shown in FIG. 1 returns to the initial state.

〔Effect of the invention〕

The repeater of the present invention starts transmitting the output of the preamplifier generator as soon as it detects the arrival of all data signals, and also writes the received data signal to the required data number PIPυ, reads it with the transmission clock, and sends the read data signal By matching the output of the preamplifier generator with the output of the preamplifier generator and cutting off the transfer output after t to the data signal read from the output of the preamble generator, not only can the total relay delay time be minimized, but also The effect is that there is no possibility of the preamble becoming discontinuous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG. 1...Reception circuit, 2...FIFO15
...... Transmission circuit, 6... Control circuit, 8.
...Preamble generator. 9...Selector. Nwo Nhen is: Tokikuri Part 2

Claims (1)

[Claims] A burst data signal having a preamble is received and sequentially written into a first-in, first-out buffer. After a predetermined number of data have been written, the data signal is read out using a read clock that is not necessarily synchronized with the write clock. a preamble generating means for generating a signal having the same pattern as the preamble using the read clock; and a preamble generating means for selectively outputting the read output of the first-in, first-out buffer when a control signal is input, and when the control signal is not input. selection means for selecting and outputting the output of the preamble generation means; and a transmission control for detecting the arrival of the data signal, transmitting the output of the selection means, detecting completion of reading from the first-in first-out buffer, and stopping transmission. means, after a predetermined time after the start of reading from the first-in, first-out buffer, a match is determined between the readout output of the first-in, first-out buffer and the output of the preamble generating means, and if they match, the control is performed until the reading of the first-in, first-out buffer is completed; A repeater characterized in that it includes a control means that outputs a signal, stops the read clock for a predetermined number of pulses when they do not match, and then makes the match determination again.