JPS62109418A - Chip-shaped delay element - Google Patents
Chip-shaped delay elementInfo
- Publication number
- JPS62109418A JPS62109418A JP24931485A JP24931485A JPS62109418A JP S62109418 A JPS62109418 A JP S62109418A JP 24931485 A JP24931485 A JP 24931485A JP 24931485 A JP24931485 A JP 24931485A JP S62109418 A JPS62109418 A JP S62109418A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- pattern
- electrode
- delay element
- comb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
薄形の誘電体基板の表面にインダクタンスパターンを形
成し、裏面に所望にレーザーカット容易な櫛形電極を形
成することにより、遅延時間可変の、小形のチップ形遅
延素子を提供する。[Detailed Description of the Invention] [Summary] By forming an inductance pattern on the front surface of a thin dielectric substrate and forming a desired comb-shaped electrode that can be easily laser cut on the back surface, a small chip type with variable delay time is created. A delay element is provided.
本発明は、インダクタンスと静電容量とを、■々回路で
設けたチップ形遅延素子に関する。The present invention relates to a chip-type delay element in which inductance and capacitance are provided in separate circuits.
近年は、高誘電率の誘電体基板の表面に、膜回路により
インダクタンスを形成し、裏面にアース電極を形成して
、静電容量を設けた小形の遅延素子が使用されている。In recent years, small delay elements have been used in which an inductance is formed by a film circuit on the front surface of a dielectric substrate with a high dielectric constant, and a ground electrode is formed on the back surface to provide capacitance.
この際、遅延時間の調整可能な遅延素子が要望されてい
る。At this time, there is a demand for a delay element whose delay time can be adjusted.
第2図は従来の遅延素子の斜視図゛であって、1は薄形
の高誘電率の誘電体、例えばアルミナよりなる誘電体基
板であって、誘電体基板1の表面に、蛇腹形のインダク
タンスパターン2を、厚膜、或いは薄膜で形成しである
。FIG. 2 is a perspective view of a conventional delay element, in which 1 is a dielectric substrate made of a thin dielectric material with a high dielectric constant, such as alumina, and a bellows-shaped dielectric substrate 1 is formed on the surface of the dielectric substrate 1. The inductance pattern 2 is formed of a thick film or a thin film.
一方、誘電体基板1の裏面の全面に、アース電極3を厚
膜、或いは薄膜で形成して、インダクタンスパターン2
との間で静電容量を設けている。On the other hand, an earth electrode 3 is formed as a thick film or a thin film on the entire back surface of the dielectric substrate 1, and an inductance pattern 2 is formed.
A capacitance is provided between the
また、インダクタンスパターン2の端末部、及びアース
電極3の所望の個所に、ビン状の外部端子4.及び外部
端子5を接着しである。Further, a bottle-shaped external terminal 4. and external terminals 5 are glued.
このような遅延素子は、外部端子4,5が、例えばスル
ーホールに挿着半田付けされて、プリント板の所望の遅
延線路部に実装され、電子装置の小形化、低コスト化の
推進に寄与している。In such a delay element, the external terminals 4 and 5 are inserted and soldered into, for example, through holes and mounted on a desired delay line portion of a printed circuit board, contributing to the miniaturization and cost reduction of electronic devices. are doing.
しかしながら、上記従来の遅延素子は、遅延時間を調整
するにあたって、異なった形状のインダクタンスパター
ンを新しく形成するより他に手段がなく、調整作業が著
しく困難であるという問題点があった。However, the conventional delay element described above has a problem in that the only way to adjust the delay time is to newly form an inductance pattern of a different shape, making the adjustment work extremely difficult.
?問題点を解決するための手段〕
上記従来の問題点を解決するため本発明は、第1図のよ
うに、誘電体基板1の表面に形成されたインダクタンス
パターン10と、誘電体基板1の裏面に形成された、薄
膜、または厚膜の櫛形電極11とを備え、インダクタン
スパターン10と櫛形電極11との間で、静電容量を設
けるようにしたものである。? Means for Solving the Problems] In order to solve the above conventional problems, the present invention, as shown in FIG. A thin film or a thick film comb-shaped electrode 11 is formed on the inductance pattern 10, and a capacitance is provided between the inductance pattern 10 and the comb-shaped electrode 11.
上記本発明の手段によれば、インダクタンスパターンl
Oの反対側の面には、静電容量を決める櫛形の電極11
を形成しである。このような櫛形の電極は、レーザ加工
により櫛歯部分を切り離すことが容易であって、静電容
量が可変である。According to the above means of the present invention, the inductance pattern l
On the opposite side of O, there is a comb-shaped electrode 11 that determines the capacitance.
It is formed. The comb-teeth portion of such a comb-shaped electrode can be easily separated by laser processing, and the capacitance is variable.
即ち、本発明のチップ形遅延素子は、静電容量を変える
ことにより、LとCの積の平方根に比例する遅延時間を
、調整することができる。That is, the chip-type delay element of the present invention can adjust the delay time proportional to the square root of the product of L and C by changing the capacitance.
以下図示実施例により、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。The present invention will be specifically explained below with reference to illustrated examples. Note that the same reference numerals indicate the same objects throughout the figures.
第1図は本発明の1実施例の斜視図であって、(a)は
表面図、fblは裏面図である。FIG. 1 is a perspective view of one embodiment of the present invention, in which (a) is a front view and fbl is a back view.
第1図において、誘電体基板1の表面には、導体パター
ンを蛇行させたインダクタンスパターン10を、厚膜、
薄膜等の膜回路により形成しである。In FIG. 1, an inductance pattern 10 having a meandering conductor pattern is formed on the surface of a dielectric substrate 1 as a thick film.
It is formed by a film circuit such as a thin film.
インダクタンスパターン10の端末部は、それぞれ誘電
体基板1の対向する端面側に設けられ、側縁に平行した
短冊形の端子電極12となっている。The terminal portions of the inductance pattern 10 are provided on opposite end surfaces of the dielectric substrate 1, and serve as strip-shaped terminal electrodes 12 parallel to the side edges.
なお、端子電極12は、誘電体基板1の表■側より側端
面を経て、裏面に延伸させ、側縁に平行した短冊形に形
成しである。The terminal electrode 12 is formed into a rectangular shape parallel to the side edge by extending from the front side of the dielectric substrate 1, through the side end face, and then to the back side.
誘電体基板1の裏面には、第1図(b)のように−・対
の端子電極12に直交する側縁近傍に、帯状の幹パター
ンを設け、幹パターンに連結して直角に多数の櫛歯を設
けて、櫛形電極11を厚膜、薄膜等の膜回路により形成
しである。On the back surface of the dielectric substrate 1, as shown in FIG. 1(b), a belt-shaped stem pattern is provided near the side edges orthogonal to the pair of terminal electrodes 12, and a large number of strips are connected to the stem pattern and arranged at right angles. The comb teeth are provided, and the comb-shaped electrode 11 is formed by a film circuit such as a thick film or a thin film.
櫛形電極11の幹パターンの一部は、誘電体基板1の端
面側に延伸して、端子電壜14となっている。A portion of the stem pattern of the comb-shaped electrode 11 extends toward the end surface of the dielectric substrate 1 to form a terminal bottle 14 .
そして、端子電極14は、誘電体基板1の裏面側より側
端面を経て、表面に延伸されている。よって、表面側で
、櫛形電極11に接続したリード端子を接続することも
可能である。The terminal electrodes 14 extend from the back side of the dielectric substrate 1 to the front side through the side end faces. Therefore, it is also possible to connect the lead terminal connected to the comb-shaped electrode 11 on the front side.
上述のように、本実施例のチップ形遅延素子は、誘電体
基板1の表面にインダクタンスパターン1゜が形成され
、裏面の櫛形電極11との間に静電容1が形成されるこ
とにより、遅延機能を存するチ・7プ形部品である。As described above, the chip-type delay element of this embodiment has an inductance pattern 1° formed on the front surface of the dielectric substrate 1, and a capacitance 1 formed between the dielectric substrate 1 and the comb-shaped electrode 11 on the back surface, thereby achieving delay. It is a chip-shaped part that has a function.
このチップ形遅延素子は、インダクタンスパターン10
側を下方にして、プリント板に載せ、プリント板の所定
のパターンにそれぞれの端子電極12゜端子電極14を
位置合わせして、半田付は接続し、プリント板に実装す
ることができる。This chip type delay element has an inductance pattern 10
The terminal electrodes 12 and 14 are placed on a printed board with the side facing downward, each terminal electrode 12° is aligned with a predetermined pattern on the printed board, and the terminal electrodes 14 are connected by soldering and mounted on the printed board.
なお、櫛形電極11側を下方にして、プリンl−t&に
実装することも容易であり、また、それぞれの電極にリ
ード端子を接続し、リード端子を所望に、例えばスルー
ホール、或いは他の接続線に直接接続して実装すことも
できる。Note that it is also easy to mount the comb-shaped electrode 11 side downward on the printer L-T&, and also connect lead terminals to each electrode and connect the lead terminals as desired, for example, through a through hole or other connection. It can also be implemented by connecting directly to the wire.
このチップ形遅延素子の遅延時間の調整は、櫛形電極1
1の選択した櫛歯を例えば根本部分、即ち第1図(bl
に示す点線M−M部分で、適宜数レーザカットする。こ
のことにより静電容量が変わり、遅延時間の調整が容易
にできる。The delay time of this chip-type delay element is adjusted by using the comb-shaped electrode 1.
1 selected comb teeth, for example, the root part, that is, FIG. 1 (bl
An appropriate number of laser cuts are performed along the dotted line M-M shown in FIG. This changes the capacitance, making it easy to adjust the delay time.
以上説明したように本発明は、誘電体基板の一方の面に
櫛形電極を設けたもので、静電容量を容易に変えること
ができ、遅延時間の調整が容易であるという、実用上で
優れた効果がある。As explained above, the present invention has a comb-shaped electrode on one side of a dielectric substrate, and has practical advantages in that the capacitance can be easily changed and the delay time can be easily adjusted. It has a positive effect.
第1図は本発明の1実施例の斜視図で、(alは表面図
、
(b)は裏面図、
第2図は従来の遅延素子の斜視図である。
図において、
1は誘電体基板、
2.10はインダクタンスパターン、
3はアース電極、
4.5は外部端子、
11は櫛形電極、
12、14は端子電極を示す。FIG. 1 is a perspective view of one embodiment of the present invention, (al is a front view, (b) is a back view, and FIG. 2 is a perspective view of a conventional delay element. In the figure, 1 is a dielectric substrate. , 2.10 is an inductance pattern, 3 is a ground electrode, 4.5 is an external terminal, 11 is a comb-shaped electrode, and 12 and 14 are terminal electrodes.
Claims (1)
ターン(10)と、 該誘電体基板(1)の裏面に形成された、薄膜、または
厚膜の櫛形電極(11)とを備え、 該インダクタンスパターン(10)と該櫛形電極(11
)との間で、静電容量が設けられてなることを特徴とす
るチップ形遅延素子。[Claims] An inductance pattern (10) formed on the surface of a dielectric substrate (1), and a thin or thick comb-shaped electrode (11) formed on the back surface of the dielectric substrate (1). and the inductance pattern (10) and the comb-shaped electrode (11).
) A chip-type delay element characterized in that a capacitance is provided between the element and the element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24931485A JPS62109418A (en) | 1985-11-07 | 1985-11-07 | Chip-shaped delay element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24931485A JPS62109418A (en) | 1985-11-07 | 1985-11-07 | Chip-shaped delay element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62109418A true JPS62109418A (en) | 1987-05-20 |
Family
ID=17191148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24931485A Pending JPS62109418A (en) | 1985-11-07 | 1985-11-07 | Chip-shaped delay element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62109418A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5585014A (en) * | 1993-06-30 | 1996-12-17 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for electrical discharge machining using variable capacitance and variable inductance |
EP0926932A2 (en) * | 1997-12-26 | 1999-06-30 | Matsushita Electric Industrial Co., Ltd. | A multi-layer circuit board including a reactance element and a method of trimming a reactance element in a circuit board |
US6864760B1 (en) | 1999-06-01 | 2005-03-08 | Murata Manufacturing Co., Ltd. | Delay line with a parallel capacitance for adjusting the delay time |
-
1985
- 1985-11-07 JP JP24931485A patent/JPS62109418A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5585014A (en) * | 1993-06-30 | 1996-12-17 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for electrical discharge machining using variable capacitance and variable inductance |
CN1063697C (en) * | 1993-06-30 | 2001-03-28 | 三菱电机株式会社 | Method and apparatus for electrical discharge machining using variable capacitance and variable inductance |
EP0926932A2 (en) * | 1997-12-26 | 1999-06-30 | Matsushita Electric Industrial Co., Ltd. | A multi-layer circuit board including a reactance element and a method of trimming a reactance element in a circuit board |
EP0926932A3 (en) * | 1997-12-26 | 1999-12-15 | Matsushita Electric Industrial Co., Ltd. | A multi-layer circuit board including a reactance element and a method of trimming a reactance element in a circuit board |
US6310527B1 (en) | 1997-12-26 | 2001-10-30 | Matsushita Electric Industrial Co., Ltd. | Multi-layer circuit board including reactance element and a method of trimming a reactance element in a circuit board |
US6864760B1 (en) | 1999-06-01 | 2005-03-08 | Murata Manufacturing Co., Ltd. | Delay line with a parallel capacitance for adjusting the delay time |
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