JPS62109289A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce an access time for read when a bit of information is '1' and to speed up the titled device by fixing the voltage level of a bit line normally. CONSTITUTION:When a semiconductor integrated circuit is in a waiting state by applying a prescribed signal on a control circuit 1, all of the word lines 4 and all of the bit lines 6 are not selected regardless of an address input signal. In such a state, a transistor 11 is not conducted, and the drain side of the transistor 11 becomes 'H' level, and a transistor 12 conducts through a signal line 13, and the charge of the bit line 6 is discharged to GND, therefore, the potential of the bit line 6 is fixed. Since the potential of the bit line is fixed at GND until the signal of the wod line is inputted, a CE access time can be reduced, when the bit of memory information is '1' a high speed semiconductor integrated circuit device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a circuit designed to shorten read time.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device. In the figure, reference numeral 1 denotes a control circuit which, by receiving an input signal at an input terminal, sets the semiconductor integrated circuit device to a readable operating state or a low power consumption standby state.

2 is an address input circuit, which connects address input terminals (AO to A
n) receives an address signal. 3 is an X decoder which outputs an X decoder output signal in response to an address input signal. 4
is the output of the X-decoder 3, which is connected to the gate electrode of the memory transistor 7 and forms a word line. The memory transistor 7 has its source side connected to GN.
D is grounded, and the drain side is connected to the Y decoder 5 through the bit line 6. Y decoder 5 is connected to address input circuit 2 and transmits the output of selected memory transistor 7 to sense amplifier 8.

The sense amplifier 8 converts the output of the memory transistor 7 into 1)''
Or it is determined to be “0” and transmitted to the output circuit 9.
Output from the output terminals (Do to Dm).

Next, the operation of the conventional device will be explained.

First, two states of the control circuit 1 will be explained. When a predetermined signal is applied to the control circuit 1 to set it in a standby state, all word lines 4 and all bit lines 6 become unselected regardless of the address input signal.

Next, when a predetermined signal is applied to the control circuit 1 to set it in an operating state, the semiconductor integrated circuit device becomes in an operating state and becomes readable.

Next, to explain the access time, when the above-mentioned semiconductor integrated circuit device which has entered the operating state by applying a predetermined signal to the control circuit 1 receives an input signal to the address input terminals (AQ to An), the address input circuit 2 generates a waveform. The signal is shaped, amplified, and transmitted to X decoder 3 and X decoder 5. X decoder 3 and X decoder 5 select word line 4 and pip I line 6 corresponding to the input signal, and
, bit line 6 selects a predetermined memory transistor 7. The memory transistor 7 has “1” in advance.
"or 0" is written, and if it is "1", the focus line 6 and GND will be conductive, and if it is "O", it will be non-conductive, and the memory information of either of these can be sensed via the bit line 6. Inform amplifier 8. The sense amplifier 8 senses ``1'' or ``0'' of the output of the memory transistor 7 and transmits it to the output circuit 9, where the output circuit 9 shapes and amplifies the waveform and outputs it to the output terminal (DoxDm). In this manner, when the semiconductor integrated circuit device is in an operating state, the readout time from receiving an address input signal until predetermined memory information is output to an output terminal is defined as an address access time, and a predetermined signal is sent to the power control circuit 1. The above-mentioned semiconductor integrated circuit device which has been added and is in a standby state,
The time during which a predetermined signal is applied to the control circuit 1 and memory information is read in order to achieve the above operating state is defined as the CE access time.

The address access time and surface access time are different when the memory information is "1" and "0", respectively. The reason why the memory information is "1" and an output corresponding to the memory information is obtained at the output terminal is because the word line 4 and the bit line 6 are selected and the memory transistor 7 is turned on and the charge on the bit line 6 is discharged to GND. memory transistor 7
This is only when the sense amplifier 8 senses the output as "1", but when the memory information obtains an output corresponding to "0", when there is no word line 4 or bit line 6,
The charge on the bit line 6 is not released to GND, and the sense amplifier 8 senses 0'', resulting in an output similar to that obtained when reading 0.

[Problem that the invention seeks to solve]

Since the conventional semiconductor integrated circuit device is configured as described above, when the memory information is "1", even if the word line 4 and the focus line 6 are selected, the memory transistor 7 is
It has been difficult to read out "1" until after the bit line 6 has been electrically conductive and the charge on the bit line 6 has been discharged, making it difficult to shorten the access time.

This invention was made to solve the above-mentioned problems, and aims to reduce the difference in access time between cases where memory information is different, and to obtain a semiconductor integrated circuit device that can shorten the access time. .

[Means for solving problems]

The semiconductor integrated circuit device according to the present invention includes a signal detection means for detecting a word line signal, and a voltage level control means for normally fixing the voltage level of the bit line and releasing the voltage level by the output of the signal detection means. It has been established.

[Effect]

In this invention, the potential of the bit line can be fixed to GND by the voltage level control means until just before the word line signal reaches the gate electrode of the memory transistor, thereby shortening the CE access time when the memory information is 1)''. As a result, the speed of the semiconductor integrated circuit device is increased.

〔Example〕

An embodiment of this invention will be described below.

FIG. 1 shows a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, in which 1 is a control circuit;
By receiving an input signal at the input terminal CE, the semiconductor integrated circuit device is set to a readable operating state or a low power consumption standby state. 2 is an address input circuit which receives address signals at address input terminals (Ao to Am). 3 is an X decoder which outputs an X decoder output signal in response to an address input signal. 4 is the output of the X decoder 3, which is connected to the gate electrode of the transistor 1) and the memory transistor 7, forming a word line. The memory transistor 7 has its source side grounded to GND, and its drain side connected to the Y decoder 5 through the pinto line 6. Y decoder 5 is connected to address input circuit 2 and transmits the output of selected memory transistor 7 to sense amplifier 8. The sense amplifier 8 determines the output of the memory transistor 7 as "1" or O, and transmits it to the output circuit 9, which outputs a signal from the output terminals (Do to Dm). 10 is a P-channel field effect The source side is connected to the first electrode, and the drain side is connected to the drain side of transistor 1).The gate voltage +i of transistor 1) is connected to word line 4, and the source side is connected to GND. The transistor 12 has its drain side connected to the bit line 6, its source side grounded to GND, and its gate electrode connected to the transistor 10.1 by the signal line 13.
connected to the drain side of the

Next, the operation will be explained.

When the semiconductor S product circuit is in a standby state by applying a predetermined signal to the control circuit 1, all word lines 4 and all bit lines 6 are not selected regardless of the address input signal. In this state, the transistor 1) becomes non-conductive, and the drain side of the transistor 1) becomes "H" level, making the transistor 12 conductive via the signal line 13, discharging the charge on the bit line 6 to GND, and causing the bit line 6 to become conductive. The potential of is fixed to GND. Next, a predetermined signal is applied to the control circuit 1 to put the circuit into an operating state, and when an address input signal is input to the address input terminals (AO to Am), the address input circuit 2 shapes and amplifies the waveform, and the X decoder 3 and Word line 4 and bit line 6 are selected by Y decoder 5. At this time, the signal on the word line 4 makes the transistor 1) conductive, so that the drain side of the transistor 1) becomes "L" level, and the signal line 13
The transistor 12 is made non-conductive via the bit line 6, and the bit line 6 is opened. As described above, by making the signal on the word line 4 reach the gate electrode of the memory transistor 7 via the gate electrode of the transistor 1), when the memory information of the memory transistor 7 is "1", the word line 4 When the signal reaches the gate electrode of the memory transistor 7, the potential of the bit line 6 becomes almost the same potential as when the memory transistor 7 is turned on, and the output of the memory transistor 7 becomes almost at the same time as the word line 4 is selected. The signal is sensed by the sense amplifier 8 and transmitted to the output circuit 9. The output circuit 9 shapes and amplifies the signal determined to be "1" by the sense amplifier 8, and outputs the signal to the output terminal (Do-
Dm).

In this embodiment, the potential of the bit line is fixed at GND until the word line signal is input, so the CE access time when memory information is "1" can be shortened, and the semiconductor Integrated circuit devices can be made faster.

In the above embodiment, a P-channel field effect transistor is provided between the first electrode and the drain of transistor 1), but a depression type transistor or a resistor is provided between the first electrode and the drain of transistor 1). It may be provided.

Further, in the above embodiment, the source of the transistor 12 is GN
Although this source is grounded to D, sense amplifier 8 is “1”.
It is sufficient if the level is such that it can be detected.

〔Effect of the invention〕

As described above, according to the present invention, by using the word line signal, the access time for reading when memory information is "1" can be shortened, and thereby the access time when memory information is "0" can be shortened. This has the effect of reducing the difference between the two and thereby increasing the speed of the semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device. ■...Control circuit, 2...Address input circuit, 3...
・X decoder, 4... word line, 5... Y decoder, 6... bit line, 7... memory transistor, 8... sense amplifier, 9... output circuit, lO
...P-channel field effect transistor, 1). 12
...Enhancement type transistor, 13...Signal line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device in which a memory element is arranged at the intersection of a word line and a bit line, a signal detection means for detecting a word line signal input to a certain memory element is usually connected to the memory element. 1. A semiconductor integrated circuit device comprising: voltage level control means for fixing a voltage level of a bit line and releasing said voltage level by an output of said signal detection means.