JPS6177196A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the cell of one element/bit for the high integration of an EEPROM by changing the electric potential of a data line above an external electric power source or below 0V when reading the information of a memory cell. CONSTITUTION:A pulse generated by the change of the address of an address buffer 81 is outputted from a control circuit 82 to a signal line 83 for bootstrap and charges a data 86 selected by a Y decoder 84, a Y switch 85 above 5V, for example to 7V by the bootstrap. The charged data line is changed in electric potential by the condition of a memory cell selected by an X decoder 88 (memory array 89). This signal change is detected by a sense amplifier 90 and outputted through an output buffer 91 to the outside. Thereby, the memory cell can be constituted with one element of a memory transistor capable of taking threshold voltages of a positive and a negative, and even if the threshold voltage of the transistor of a non selecting memory cell belonging to the same data line is negative, the information of a selecting cell can be correctly read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory integrated circuit, and particularly to a semiconductor memory device having a novel reading means when reading information from a memory.

[Background of the invention]

Conventionally, in a semi-driving integrated circuit equipped with a memory, when reading the contents of the memory, a voltage is applied to a selected word line (the word line to which the memory cell to be read belongs), and a voltage is applied to unselected word lines. A method has been adopted in which no voltage is applied. In this case, the memory cells include at least one enhancement type transistor, and no current flows through unselected memory cells. Such conventional examples are shown in FIGS. 1 to 4. Figure 1 shows an ordinary 1 transistor + 1 canon (side-type) dynamic RAM memory cell, and the read transistor T1 has a voltage of V~〉0. Figure 2 shows an ordinary static RAM memory cell with a high resistance polycrystalline silicon load. In a RAM memory cell, the V of the read transistor T,, T,.

Similarly, v −b >O. Figure 3 shows the normal [
The memory cell of the EPROM (in this case, the memory element itself called FAMO5 is an enhancement type transistor), that is, vtk of T6 is VLh>0. Figure 4 shows 2 disclosed in Japanese Patent Application Laid-Open No. 54-57875.
In the element/bit type EEPROM memory cell, 1 and 1 of the memory element T7 take positive to negative values, but the read transistor T and (7) VLh satisfy vtk>O.

As described above, in these conventional memory cells, it is necessary to use an enhancement type read transistor in order to prevent current from flowing to non-selected memory cells.

[Purpose of the invention]

The above-mentioned limitations may be detrimental to improving the performance of integrated circuits.6 The purpose of the present invention is to
The object of the present invention is to provide a 1 element/bit cell for highly integrated PROM.

[Summary of the invention]

When changing the 2-element/bit type memory cell shown in FIG. 4 to the 1-element/bit type memory cell shown in FIG. 5, the threshold voltage of the memory element Tg has a positive to negative value depending on the write information. Therefore, leakage current flows through memory cells with negative threshold voltages even if they are not selected. In other words, in the conventional method of setting the unselected word line to 0 potential and applying a voltage to the selected word line to read out information in the memory cell, a single element/bit type using memory elements with positive and negative threshold voltages is used. memory cells are difficult to realize.

Therefore, the inventors have already proposed a memory cell that eliminates the drawbacks of the prior art and does not require an enhancement type transistor.

This outline will be explained below with reference to FIG.

This feature is based on the conventional wisdom that a voltage is applied between the word line (gate of the transistor) Wo of the selected memory cell and the source S of the transistor, and the voltage is applied between the unselected word line W2 and the source S1. The first feature lies in breaking away from the concept of "no voltage is applied", that is, the first feature is that the source S0. The point is to apply a voltage to S. This makes it possible to prevent current from flowing through the secondary even if the threshold voltage of an unselected memory transistor is negative. Therefore, the information of the selected cell can be read accurately.

Furthermore, a second feature is that at least a voltage comparable to the voltage applied to unselected cells is applied between the substrate of the memory cell (or the well in which the memory cell is provided) Su and the source 5tyS2 of the memory transistor during reading. be. By doing so, in the memory transistor of the unselected memory cell to which a voltage is applied to the gate, the voltage applied to the gate insulating film can be suppressed to about the threshold voltage Vtk. [In a memory transistor used in an EEFROM, when a voltage is applied to the gate insulating film, the amount of charge stored in the insulating film changes. Therefore, this second
The voltage applied to the gate insulating film of the memory transistor is V. A method of suppressing the amount of noise to a certain extent is essential for EEFROM memory devices.

[Embodiments of the invention]

Now, when the above voltage relationship is satisfied, several cases can be considered depending on how the source potential of the memory transistor is set and whether the memory element is an N-channel or a P-channel.

This is shown in Table 1 for the memory array of FIG.

In Table 1, vo. is selected for convenience and can be freely selected depending on the vtk variation range of the memory element. Hereinafter, the reading method will be described using cases 2 and 4 in the table, which can be operated only with VC, as examples.

Nα1. It is clear that the method of applying voltage to unselected word lines can also be implemented in the method of N(13).

Table 1 (For Ha 2 in Table 1) For Nα2 As shown in Table 1, in order to prevent voltage from being applied to the gate insulating film of the memory element during reading, the data lines (Dl, D2) must be ■ Potential. . It is necessary to operate above. However, vo. When operating the sense system at a voltage higher than that, there are problems with current consumption, etc.
It becomes difficult to use high-voltage power supplies generated within the chip. Therefore, as shown in FIG. 7, when the data line is once charged to Vcc or higher at time t1 by capacitive coupling (by the so-called bootstrap effect) and the word line is selected at t2, the 0N10FF of the memory element is (
"1"/'"O") Depending on the situation, it is possible to detect whether the charge is extracted or not.
Make it work with co.

(In the case of Nα4 in Table 1) In the case of Nα4, as similarly shown in Table 1, it is necessary to operate the data line potential at 0 V or less. In this case, the data line is charged to below ~10° by bootstrapping, and the change in potential is detected.

Embodiment 1) Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 8, 9, and 10. FIG. 8 is a diagram showing an overall outline of this embodiment.

In this figure, a pulse generated by a change in the address of an address buffer 81 is output from a control circuit 82 to a bootstrap signal line 83, and a predetermined number of data lines selected by a Y decoder 84 to a Y switch 85 are output! 86(
When a data line (usually 8 bits in an 8-bit configuration and 16 bits in a 16-bit configuration) is charged to 5V or more, for example 7V, by bootstrapping (bootstrap capacitance 87), the X-decoder 88 The state of the selected memory cell (memory array 89) connected to this data line (conduction state II
I+ or non-conducting state II OI! ), the potential changes as shown in FIG. 7 above. This signal change is detected by the sense amplifier 90 and outputted to the outside through the output buffer 91. FIG. 9 shows a specific circuit configuration, and FIG. 10 shows temporal changes in the potential of each numbered line.

Various types of sense amplifiers 90 can be considered, for example,
The differential sense amplifier shown here is designed to increase the sensitivity of the sense amplifier by increasing the threshold voltage of the transistors T, , T, in the input section.

Embodiment 2) Although the above embodiment has shown an example in which an N-channel memory element is used, an embodiment in which a P-channel memory cell is used will now be described with reference to FIGS. 11 and 12. In this case, the data line 3 is charged to a negative voltage, e.g. -2v, via the bootstrap capacitor (capacitor xk connected to 7), and when the word Ml is selected and goes from 5v to O■, the memory The change in potential differs depending on the state of the cell (conducting or non-conducting). This was input to the gate of an N-channel MOS transistor T□ having a negative threshold voltage and connected to a sense amplifier. Negative voltage fluctuations on the data line are converted into positive voltage fluctuations by the transistor T11, and detected by the sense amplifier.

Although only two types of sense amplifiers have been shown in the above embodiments, the present invention is not limited to this, and many types of sense amplifiers can be considered. Therefore, the gist of the present invention is to
In short, vo. It is characterized in that the input of the sense amplifier whose power sources are Vcc and ov is a data line temporarily charged to a voltage higher than Vcc or lower than 0V. In addition to what is shown above, a dummy cell is placed in the portion corresponding to V r * f of the differential sense amplifier, and a current of approximately 1/2 of that of the memory cell flows, and the potential of this dummy data line and the original data line are It is also possible to detect slight potential differences.

〔Effect of the invention〕

According to the present invention, a memory cell can be configured with one memory transistor element that can take positive and negative threshold voltages, and even if the threshold voltage of the transistor of an unselected memory cell belonging to the same data line is negative, the selected cell information can be read accurately.

Therefore, it is possible to realize a highly integrated EEPROM.

[Brief explanation of the drawing]

FIGS. 1, 2, 3, and 4 are circuit diagrams showing conventional memory memo and recell, and FIGS. 5 and 6. 8, 9, and 11 are circuit diagrams showing a memory cell, a memory array, and a reading method used in the present invention, and FIG.
10 and 12 are voltage waveform diagrams for explaining the present invention. 1, W, w,, w, . . . word line, 2. S, S,,S
2... Source (ground) line, 3. D, D,, D,,
D￥;

Claims (1)

[Claims] 1. In an integrated circuit having a memory array and a peripheral circuit on the same chip, when reading information from a memory cell, the potential of a data line is changed by an external power supply V_c_c or more or 0V or less. Features of semiconductor memory integrated circuits. 2. In the semiconductor memory integrated circuit according to claim 1, the potential of the data line from which information of the memory cell is read is set to an external power supply voltage V_c_ before the memory cell is selected.
1. A semiconductor memory integrated circuit comprising means for pre-charging to a voltage higher than or equal to c or lower than 0V and means for detecting a change in the potential of the data line. 3. The semiconductor memory integrated circuit according to claim 2, comprising means for detecting the potential of the data line that changes at a power supply voltage V_c_c or higher or 0V or lower, and the means operates at an external power supply voltage V_c_c and 0V. A semiconductor memory integrated circuit characterized in that it is configured as follows.