JPS62109191U - - Google Patents
Info
- Publication number
- JPS62109191U JPS62109191U JP20126585U JP20126585U JPS62109191U JP S62109191 U JPS62109191 U JP S62109191U JP 20126585 U JP20126585 U JP 20126585U JP 20126585 U JP20126585 U JP 20126585U JP S62109191 U JPS62109191 U JP S62109191U
- Authority
- JP
- Japan
- Prior art keywords
- ttl
- signal
- analog
- buffer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims 1
- 238000007493 shaping process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第1図はこの考案の入力信号切替回路の実施例
を示す回路図、第2図はCPUより出力される同
期信号の波形図、第3図は先行技術の回路図であ
る。
2…TTLバツフア、3…アナログバツフア、
7…入力信号切替回路。
FIG. 1 is a circuit diagram showing an embodiment of the input signal switching circuit of this invention, FIG. 2 is a waveform diagram of a synchronizing signal output from a CPU, and FIG. 3 is a circuit diagram of a prior art. 2...TTL buffer, 3...analog buffer,
7...Input signal switching circuit.
Claims (1)
映像信号のTTL量の信号を受けて該TTL量の
信号のスレツシユホールドレベルを決定し波形整
形し、波形整形された信号を増幅等しTTL映像
信号を出力するTTLバツフアと、 前記映像信号のアナログ量の信号を受けて増幅
等しアナログ映像信号を出力するアナログバツフ
アと、 該アナログバツフアより出力されたアナログ映
像信号と前記TTLバツフアより出力されたTT
L映像信号とCPUより出力される同期信号の相
異を受けて該同期信号によりアナログ映像信号と
TTL映像信号の出力の切替えと同時にもしくは
単独に入力インピーダンスを切替える入力信号切
替回路とを備えて構成したことを特徴とする映像
入力信号切替回路。 2 前記入力信号切替回路は、前記TTLバツフ
アの入力部に前記TTLバツフアの入力インピー
ダンスをマツチングさせる抵抗を介して接地させ
たTTLマツチング抵抗器と、 前記アナログバツフアの入力部に該アナログバ
ツフアの入力インピーダンスをマツチングさせる
抵抗の一端側を接続したアナログマツチング抵抗
器と、 該アナログマツチング抵抗器の他端側の接地を
前記同期信号によりオンオフ制御するスイツチン
グ部によつて構成したことを特徴とする実用新案
登録請求の範囲第1項に記載の映像入力信号切替
回路。 3 前記入力信号切替回路は、前記TTLバツフ
ア及び前記アナログバツフアの駆動電源の給電を
も切替えることを特徴とする実用新案登録請求の
範囲第1項乃至第2項に記載の映像入力信号切替
回路。[Claims for Utility Model Registration] 1. Receiving a TTL amount of video signal that drives a display device such as a CRT or liquid crystal, determining the threshold level of the TTL amount signal and shaping the waveform. a TTL buffer that amplifies a signal and outputs a TTL video signal; an analog buffer that receives and amplifies an analog signal of the video signal and outputs an analog video signal; and an analog video output from the analog buffer. signal and TT output from the TTL buffer
An input signal switching circuit that receives the difference between the L video signal and the synchronization signal output from the CPU and switches the input impedance simultaneously or independently by switching the output of the analog video signal and the TTL video signal based on the synchronization signal. A video input signal switching circuit characterized by: 2. The input signal switching circuit includes a TTL matching resistor grounded to the input part of the TTL buffer via a resistor that matches the input impedance of the TTL buffer, and a TTL matching resistor grounded to the input part of the analog buffer via a resistor that matches the input impedance of the TTL buffer. It is characterized by comprising an analog matching resistor connected to one end of a resistor for matching input impedances, and a switching section that controls on/off the grounding of the other end of the analog matching resistor using the synchronization signal. A video input signal switching circuit according to claim 1 of the utility model registration claim. 3. The video input signal switching circuit according to claim 1 or 2, wherein the input signal switching circuit also switches the power supply for driving the TTL buffer and the analog buffer. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20126585U JPS62109191U (en) | 1985-12-26 | 1985-12-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20126585U JPS62109191U (en) | 1985-12-26 | 1985-12-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62109191U true JPS62109191U (en) | 1987-07-11 |
Family
ID=31164554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20126585U Pending JPS62109191U (en) | 1985-12-26 | 1985-12-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62109191U (en) |
-
1985
- 1985-12-26 JP JP20126585U patent/JPS62109191U/ja active Pending
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