JPS63142993U - - Google Patents

Info

Publication number
JPS63142993U
JPS63142993U JP3522987U JP3522987U JPS63142993U JP S63142993 U JPS63142993 U JP S63142993U JP 3522987 U JP3522987 U JP 3522987U JP 3522987 U JP3522987 U JP 3522987U JP S63142993 U JPS63142993 U JP S63142993U
Authority
JP
Japan
Prior art keywords
microphone
terminal
circuit
amplifier circuit
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3522987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3522987U priority Critical patent/JPS63142993U/ja
Publication of JPS63142993U publication Critical patent/JPS63142993U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は従来のマイクアンプ回路の一例を示す回路図
である。 1……マイクロフオン、6……外部入力ジヤツ
ク、12……音声信号処理回路、13……オペア
ンプ、18……プルアツプ抵抗、19……トラン
ジスタ、20……FET、25……マイクアンプ
回路、31……加算回路、32……ステレオタイ
プのマイク入力ジヤツク。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing an example of a conventional microphone amplifier circuit. 1... Microphone, 6... External input jack, 12... Audio signal processing circuit, 13... Operational amplifier, 18... Pull-up resistor, 19... Transistor, 20... FET, 25... Microphone amplifier circuit, 31 ... Addition circuit, 32 ... Stereo type microphone input jack.

Claims (1)

【実用新案登録請求の範囲】 着脱可能なマイクロフオンから導かれる音声信
号を増幅した信号を加算回路の一方の入力端に供
給するとともに、他の音響機器を接続するための
外部入力端子から導かれる音声信号を前記加算回
路の他方の入力端に供給し、前記加算回路の出力
信号を音声信号処理回路へ導出するマイクアンプ
回路において、 前記マイクロフオンの挿入時に一方のチヤンネ
ル端子が接地状態となるステレオタイプのマイク
ジヤツクと、 前記マイクジヤツクの他方のチヤンネル端子に
接続されたマイクアンプ回路と、 前記マイクアンプ回路の出力側と前記加算回路
の一方の入力端を結ぶ電路に介挿されたアナログ
スイツチと、 前記マイクジヤツクの一方のチヤンネル端子に
接続され、該端子の接地時に前記アナログスイツ
チをオン制御し且つ非接地時に前記アナログスイ
ツチをオフ制御するスイツチ制御回路とを備えた
ことを特徴とするマイクアンプ回路。
[Claims for Utility Model Registration] A signal obtained by amplifying the audio signal led from a detachable microphone is supplied to one input terminal of the adder circuit, and the signal is also led from an external input terminal for connecting other audio equipment. In a microphone amplifier circuit that supplies an audio signal to the other input terminal of the adder circuit and derives an output signal of the adder circuit to an audio signal processing circuit, one channel terminal is grounded when the microphone is inserted. a microphone jack of the above-mentioned type; a microphone amplifier circuit connected to the other channel terminal of the microphone jack; an analog switch inserted in an electric line connecting the output side of the microphone amplifier circuit and one input end of the adder circuit; A microphone amplifier circuit comprising: a switch control circuit connected to one channel terminal of a microphone jack, which controls the analog switch to turn on when the terminal is grounded, and controls the analog switch to turn off when the terminal is not grounded.
JP3522987U 1987-03-12 1987-03-12 Pending JPS63142993U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3522987U JPS63142993U (en) 1987-03-12 1987-03-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3522987U JPS63142993U (en) 1987-03-12 1987-03-12

Publications (1)

Publication Number Publication Date
JPS63142993U true JPS63142993U (en) 1988-09-20

Family

ID=30844528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3522987U Pending JPS63142993U (en) 1987-03-12 1987-03-12

Country Status (1)

Country Link
JP (1) JPS63142993U (en)

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