JPS6452399U - - Google Patents
Info
- Publication number
- JPS6452399U JPS6452399U JP14759887U JP14759887U JPS6452399U JP S6452399 U JPS6452399 U JP S6452399U JP 14759887 U JP14759887 U JP 14759887U JP 14759887 U JP14759887 U JP 14759887U JP S6452399 U JPS6452399 U JP S6452399U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- reference potential
- detection resistor
- speaker
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 238000009499 grossing Methods 0.000 claims description 3
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案に係るステレオ音声出力回路の
一実施例を示す回路図、第２図は従来のステレオ
音声出力回路の一例を示す回路図である。
１……音量・音質・バランス制御回路、２……
音声増幅回路、３……右スピーカ、４……左スピ
ーカ、５……電源回路、１５……バランス制御端
子、ＶＲ……可変抵抗器、Ｒ３１……検出用抵抗
器、Ｒ４１……検出用抵抗器、Ｄ３２，４２……
整流用ダイオード、Ｃ３３，４３……平滑コンデ
ンサ、Ｑ３４，４４……トランジスタ、Ｑ４５…
…トランジスタ。
FIG. 1 is a circuit diagram showing an embodiment of a stereo audio output circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional stereo audio output circuit. 1...Volume/sound quality/balance control circuit, 2...
Audio amplification circuit, 3...Right speaker, 4...Left speaker, 5...Power supply circuit, 15...Balance control terminal, VR...Variable resistor, R31 ...Detection resistor, R41 ...Detection Resistor for D32 , 42 ...
Rectifying diode, C 33 , 43 ... Smoothing capacitor, Q 34 , 44 ... Transistor, Q 45 ...
...transistor.
Claims (1)
子に印加された直流電圧に基づき、前記ステレオ
音声信号の左右のバランスを制御する音量・音質
・バランスの制御回路と、 この制御回路からの左右の信号を電力増幅する
ステレオ音声出力回路と、 このステレオ音声出力回路に一端を接続した左
右一対のスピーカの他端と基準電位との間に接続
され、右スピーカと左スピーカの入力を検出する
それぞれ第１の検出抵抗及び第２の検出抵抗と、 右スピーカと第１の検出抵抗との接続点の出力
が整流・平滑回路を介してベースに供給され、コ
レクタは前記バランス制御端子に接続され、エミ
ツタは基準電位と接続し、スイツチ動作を行なう
第１の制御トランジスタと、 左スピーカと第２の検出抵抗との接続点の出力
が整流・平滑回路を介してベースに供給され、コ
レクタは第３の抵抗の一端と接続され、エミツタ
は基準電位と接続し、スイツチ動作をおこなう第
２の制御トランジスタと、 ベースが第２のトランジスタに接続した前記第
３の抵抗の他端と接続され、更に直流電圧源端子
と抵抗を介して接続され、エミツタは直流電圧源
端子と、コレクタはバランス制御端子に接続され
た第３の制御トランジスタとを具備したことを特
徴とするステレオ音声出力回路。[Claims for Utility Model Registration] A volume/sound quality/balance control circuit that controls the left-right balance of an input stereo audio signal based on a DC voltage applied to a balance control terminal; A stereo audio output circuit that amplifies the power of the left and right signals from the circuit, and a pair of left and right speakers, one end of which is connected to this stereo audio output circuit, is connected between the other ends of the pair of left and right speakers and a reference potential, and the input of the right speaker and left speaker is connected to the reference potential. The output of the connection point between the first detection resistor and the second detection resistor, which detect the right speaker and the first detection resistor, respectively, is supplied to the base via a rectifier/smoothing circuit, and the collector is connected to the balance control terminal. The emitter is connected to a reference potential, and the output from the connection point between the first control transistor that performs a switching operation, the left speaker and the second detection resistor is supplied to the base via a rectifier/smoothing circuit. The collector is connected to one end of a third resistor, the emitter is connected to a reference potential, and the second control transistor that performs a switch operation is connected to the other end of the third resistor whose base is connected to the second transistor. and a third control transistor connected to a DC voltage source terminal via a resistor, whose emitter is connected to the DC voltage source terminal, and whose collector is connected to a balance control terminal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14759887U JPS6452399U (en) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14759887U JPS6452399U (en) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6452399U true JPS6452399U (en) | 1989-03-31 |
Family
ID=31418149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14759887U Pending JPS6452399U (en) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6452399U (en) |
-
1987
- 1987-09-29 JP JP14759887U patent/JPS6452399U/ja active Pending
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