JPS62107524A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To set the frequency of a count clock lower by forming two control signals whose timing of the count clock differs by 1/2 period from each other to a current switch controlling a current source of an integration device and turning off the current switch at the timing of a selected control signal. CONSTITUTION:Integration is applied for a current I0 from a current source 6 corresponding to the count time of a data of high-order 8-bit preset to a high-order bit counter 11 and integration is applied for a current i0 from a current source 8 corresponding to the count time of a data of 5-bit of low-order 2SB-6SB preset to a low-order bit counter 12. Thus, an analog value corresponding to an input digital data is obtained. Then the timing turning off a switch circuit controlling the current value of the current source 8 is controlled by an LSB data, and when the LSB data is '0', the switch circuit 7 is turned off at the trailing of the count clock CK, and when the LSB data is 1, the switch circuit 7 is turned off at the trailing of the count clock CK.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an integral type D/A suitable for converting digital audio signals to analog audio signals.
Concerning converters.

[Summary of the invention]

The present invention is an integral type D/A suitable for converting a digital audio signal into an analog audio signal.
In the converter, by varying the timing of the control signal of the current switch that controls the current source of the integrator by two cycles in accordance with the data of the least significant bit of the input digital data, the required conversion accuracy is achieved. It is possible to obtain the desired conversion accuracy with hardware that has one bit less than the hardware, and enables high-speed operation and highly accurate conversion.

[Conventional technology]

FIG. 6 shows an example of a conventional integral type D/A converter. In FIG. 6, 51 indicates an operational amplifier, and a capacitor 52 is connected between the output terminal of the operational amplifier 51 and its inverting input terminal to constitute an integrator, and the output terminal of the operational amplifier 5] and its inverting input terminal are connected. A switch circuit 53 is connected between the terminals. An output terminal 54 is derived from the output terminal of the operational amplifier 51. A non-inverting input terminal of operational amplifier 51 is grounded. An inverted input terminal of the operational amplifier 51 is connected to one end of a current source 56 via a switch circuit 55. The other end of current source 56 is grounded.

A timing control signal is supplied to terminal 57.

This timing control signal is supplied to the switch circuit 53 and also to the counter 58.

A count clock is supplied to the counter 58 from a clock input terminal 59.

In FIG. 7, a timing control circuit supplied to terminal 57 causes time t. When the switch circuit 53 is turned on during o'''''to+, the charge stored in the capacitor 52 is discharged. As a result, the output of the operational amplifier 51 drops to a predetermined level Vr as shown in FIG. During this time, the counter 58 is preset with digital data.

At time to+, the switch circuit 53 is turned off, the switch circuit 55 is turned on, and the counter 58 counts the clocks supplied to the clock input terminal 59. When the switch circuit 55 is turned on, integration by the current source 56 is started, and the output of the operational amplifier 51 increases as shown at No. 7M.

When a carry is output from the counter 58 at time toz, the switch circuit 55 is turned off and the integration operation is stopped. Therefore, the current source 56 performs integration for a time corresponding to the digital data preset in the counter 58. Thereby, an analog signal corresponding to the input digital data preset in the counter 58 can be obtained from the output terminal 54.

By the way, in the above-mentioned conventional integral type D/A converter,
When performing D/A conversion of a digital audio signal, it is necessary to set the frequency of the clock supplied to the counter 58 to a high frequency.

For example, if the input data has a sampling frequency of 44. IKf
If iz is 14-bit data, the conversion time is (1/44.1KHz) x 'A= 11.3 μ
It becomes S. In order to enable the 14-bit counter 58 to count until it is full within this conversion time, it is necessary to set the frequency of the count clock supplied to the counter 58 to several G fly.

It is difficult to operate the counter 58 with such a high frequency count clock. Therefore, for example, Japanese Patent Application Publication No. 57-99821, Japanese Patent Application Publication No. 58-60823
As shown in the publication, the input digital data is divided into upper bits and lower bits, and presented to the upper bit counter and lower bit counter, respectively, and the upper bit counter and the lower bit counter are divided by two current sources weighted according to the number of bits. A D/A converter has been proposed in which the frequency of a count clock can be lowered by performing integration according to upper bit data and lower bit data preset in a lower bit counter.

FIG. 8 shows an example of this type of D/A converter. In FIG. 8, 101 indicates an operational amplifier, and a capacitor 102 is connected between the output terminal of the operational amplifier 101 and its inverting input terminal to constitute an integrator.
A switch circuit 103 is connected between the output terminal of operational amplifier 101 and its inverting input terminal. Operational amplifier 101
An output terminal 104 is derived from the output terminal of. A non-inverting input terminal of operational amplifier 101 is grounded. Operational amplifier 1
The inverting input terminal of 01 passes through the sui-nochi circuit 105, and the current value is I. The current source 1 is connected to the current source 106 with a current value of 11° via the switch circuit 107.
Connected to 08. The other ends of current sources 106 and 108 are grounded.

The switch circuit 103 is controlled on/off by a discharge clock supplied from a timing control circuit 110. When the switch circuit 103 is turned on, the charge stored in the capacitor 102 is discharged, and the output of the operational amplifier 101 drops to a predetermined level. During this time, the input digital data is divided into upper bits and lower bits, the upper bit data is presented to the upper bit counter 111, and the lower bit data is presented to the lower bit counter 112. .

When the switch circuit 103 is turned off, the switch circuit 10
5 and 107 are turned on, and the integration operation by current sources 106 and 108 is started. For example, when the input digital data is 14 bits and is divided into upper 8 bits and lower 6 bits, the ratio I of the current values of current source 106 and current source 108 is
10/iIo is summer. /+1°-2″'-64.

When a carry is output from the upper bit counter 111 and the lower bit counter 112, the switch circuit 10
5 and 107 are respectively turned off.

Therefore, the switch circuit 105 is turned on for the count time of the upper bit counter 111, integration is performed by the current source 11o, the switch circuit 107 is turned on for the count time of the lower bit counter 112, and the i+
Integration is performed by a current source o.

The integral output VIO obtained from the operational amplifier 101 is expressed as V+o, where C is the capacitance of the capacitor 102, T is the count time of the upper bit counter 111 (8 vias), and T2 is the count time of the lower bit counter 112 (36 bits). =(1/C)I +oT+ +(1/C)i
+oTz. Since the ratio of the current values of the current source 106 and the current source 108 is set to 1+o/i+o=26=64, an analog value corresponding to the input digital data can be obtained from this integral output VH.

If the count period is τ1o, the Vth analog value when the upper bit counter 111 and the lower bit counter 112 count until they are full is 8 bits for the upper bit counter 111.

Since the lower bit counter 112 is 6 bits, Vz= (1/C)1+oτto(281)+(1/C
)i+oτ1. (26-1) −j+oτ+o/C (2” 1), and the I LSB voltage value is 2′4 as i.τ./C.
D/A conversion with step resolution becomes possible.

[Problem that the invention seeks to solve]

Assume that a digital audio signal having a sampling frequency of 44 degrees IKHz and a quantization pitch of 1 to several 14 bits is subjected to D/A conversion using the conventional integral type D/A converter shown in FIG. 8 mentioned above. The conversion time at this time is
As mentioned above, (1/44.1KHz) x (%) = 11.3
It becomes μs. The number of bits of the upper bit counter 111 is set to 8 bits, and the number of bits of the lower bit counter 112 is set to 6 bits.
In the case of bits, the count number of the upper bit counter 111 when counting until it is full is (2''-1), and the count number of the lower bit counter 111 is (26-1).

The count clocks of the upper focus counter 111 and the lower bit counter 112 need to be set so that they can count as many as (2e-1) and (2b-1) within the above conversion time. That is, in this case, it is necessary to set the frequency of the count clock so that the count number (28-1) of the upper bit counter 111, which has a large count number, can be counted during the conversion time of 11.3 μs. Therefore, the frequency of the count clock is 2
It is necessary to set the frequency to 2.5792 MHz or higher, and there is a problem that the frequency of the count clock becomes high.

Further, in the conventional D/A converter described above, it is necessary to set the ratio of the current values of the current sources 106 and 108 of the integrator to (2'=64). When the ratio of current values is large, it becomes difficult to realize a current source with a highly accurate current ratio.

By dividing the input digital data into the upper 7 bits and the lower 7 bits, the frequency of the count clock can be reduced by 1.
It is sufficient to set it to 1.2896 MHz or higher, and the frequency of the count clock can be lowered. However, in such a configuration, it is necessary to set the ratio of the current values of the two current sources of the integrator to (27=128). If the ratio of current values becomes large in this way, it becomes impossible to obtain high accuracy.

Therefore, an object of the present invention is to provide a D/A converter in which the frequency of the count clock can be set low.

Another object of the present invention is to provide a D/A converter that can set the ratio of current values of the current sources of the integrator to a small value and obtain high accuracy.

Still another object of the present invention is to provide a D/A converter 11 that can be realized by a C-MO3 configuration and has reduced power consumption.

Means for Solving Problem C] The present invention provides an integral D/A converter in which the current switches 7 that control the current sources 8 of the integrators 1 and 2 have two cycle timings of count clocks that are different from each other. 2
The present invention is characterized in that two control signals are formed, one of the two control signals is selected according to the data of the least significant bit of the input digital data, and the current switcher is turned off at the timing of the selected control signal. This is a D/A converter.

[Effect]

Input digital data is divided into upper bits and lower bits and preset into an upper bit counter 11 and a lower bit counter 12.

The lower bit counter 12 is a counter with one bit less than the input data. The switch circuit 5 is controlled in accordance with the count time of the upper bit counter 11, and the current source 6 performs integration. The switch circuit 7 is controlled according to the count time of the lower bit counter 12, and the current source 8 performs integration. At this time, L
The timing at which the switch circuit 7 is turned off is controlled in accordance with the SB data so that the timing differs by a two-power count period. This provides resolution such as LSB phase.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, l is an operational amplifier. A capacitor 2 is connected between the output terminal of the operational term width H1 and its inverting input terminal to form an integrator, and a switch circuit 3 is connected between the output terminal of the operational amplifier 1 and its inverting input terminal. Ru. An output terminal 4 is derived from the output terminal of the operational amplifier 1. A non-inverting input terminal of operational amplifier 1 is grounded.

An inverting input terminal of the operational amplifier 1 is connected to a current source 6 via a switch circuit 5 and to a current source 8 via a switch circuit 7. The other ends of current source 6 and current source 8 are grounded. Current value of current source 5 ■. and the current value i of the current source 8. The ratio is set to be To/lo=2S=32.

The switch circuit 3 is controlled on/off by a discharge clock Pd supplied from the timing control circuit 10. This discharge clock Pd is
As shown in FIG. 2, the signal is output in synchronization with the word clock (FIG. 2A). When the switch circuit 3 is turned on, the charge stored in the capacitor 2 is discharged through the switch circuit 3. During this time, the 14-pin digital data is divided into upper 8 bits and lower 6 bits, the upper 8 bits of data are preset to the upper bit counter 11, and the lower 5 bits of data are preset to the lower bit counter 12, which is shown surrounded by a broken line. At the same time, LSB data is supplied to the terminal 13.

The upper bit counter 11 is composed of an 8-bit counter circuit. The upper 8 bits of input data are preset into the 8-bit counter. At the fall of the discharge clock Pd, the timing control circuit 10 supplies the count clock CK to the upper bit counter 11 to start counting, and at the same time, the control signal P is supplied to the switch circuit 5, and the switch circuit 5 is turned on. be done. While the switch circuit 5 is on, the current source 6 performs integration. When the high-order bit counter 11 counts the power output clocks CK until it is full,
The switch circuit 5 is turned off by the control signal P, and the integration is completed.

The lower bit 2 bit counter 12 is constituted by a 5-bit counter consisting of D clip-flops 22-27 that perform toggle operations. Among the lower 6 bits of data, data 23B to 63B are sent to D flip-flow knobs 22 to 26, respectively, forming a counter circuit. LSB data is supplied to terminal 13. Falling time c++ of discharge clock Pd (Fig. 2B)
Then, as shown in FIG. 2C, the cent signal Ps is output from the timing control circuit IO. This set signal Ps is supplied to an RS flip-flop composed of a NOR gate 14 and a NOR gate 15. This cent signal P
At the rising edge of s, as shown in Figure 2E, NOR gate 1
An RS flip-flop consisting of 4 and 15 is sent. This NOR gate consists of ]4 and ]5.
The output of the S flip-flop is supplied to the switch circuit 7 as a control signal P2. When the control signal p2 (FIG. 2E) becomes high level, the switch circuit 7 is turned on and the integration by the current source 8 is started.

In addition, an RS configured by NOR gates 14 and 15
When the flip-flop is set, a count clock CK is supplied from the timing control circuit 10 to a counter circuit made up of D flip-flops 22 to 27 via an ANDNO gate.

This count clock CK causes the data of the lower 23B to 65B, which has been presented to the counter circuit, to be counted up. When the counter circuit made up of D flip-flops 22 to 27 counts clocks CK until it is full, the output of the D flip-flop 27 for carry detection becomes high level.

The outputs of the D flip-flops 122 to 26 and the inverted output of the D flip-flop 27 for carry detection are connected to the NOR case 1.
28, and when the output of the NOR gate 28 becomes high level, it is detected that the lower hit data of 23B to 63B presented to the D flip-flops 22 to 26 have been counted until they are full.

The output of NOR gate 28 is supplied to D clip-flop 29. The D flip-flop 29 is supplied with a count clock CK. The output of the D flip-flop 29 is supplied to a D clip-flop 30 and also to a switch circuit 31. The D flip-flop 30 is supplied with an opposite phase count clock α via an inverter 33. The output of the D flip-flop 30 is supplied to a switch circuit 32.

LSB data is supplied to the switch circuit 31 via the terminal 13 and the inverter 34, and the switch circuits 31 and 3
2 in response to the LSB data supplied to terminal 13, I!
I 4flll. When the LSB data is 0, the switch circuit 31 is turned on and the switch circuit 32 is turned off. When the LSB data is 1, the switch circuit 32
is turned on, and the switch circuit 31 is turned off.

When the switch circuit 31 is turned on, the output of the D flip-flop 29 is sent to the NOR gate 14 as a reset signal Pr.
and 15 RS flip-flops.

When the switch/switch circuit 32 is turned on, the output of the D flip-flop 30 is sent to the NOR gate 1 as a reset signal Pr.
4 and 15 RS flip-flops.

The D flip-flop 30 is supplied with an anti-phase count clock. Therefore, as shown in FIG. 3B, the reset signal Pr supplied to the RS flip-flop via the switch circuit 31 is
In contrast, the reset node signal Pr supplied to the RS flip-flop via the switch circuit 32 is output in synchronization with the rising edge of the count clock CK as shown in FIG. 3C. Output in synchronization with the falling edge.

In FIG. 2, the reset signal Pr becomes NOR at time t12.
When the signal is supplied to the RS flip-flop consisting of gates 14 and 15 and the RS flip-flop is reset, the control signal P2 becomes low level, as shown in FIG. When the control signal P2 becomes low level, the switch circuit 7
is turned off, and the integration by the current source 8 is completed.

In this way, 1! corresponding to the count time of the upper 4i78 bits of data preset in the upper bit counter 11! ■ Due to source 6. Integration is performed with a current of 10 by the current source 8 corresponding to the count time of the 5-bit data of the lower 25B to 63B recently sent to the lower bit counter 12.

The ratio of the current values of current source 6 and current tA8 is 1o/io
=2' =32, so that an analog value corresponding to the input digital data can be obtained. The timing of turning off the switch circuit 7 that controls the current value of the current source 8 is controlled by the LSB data.
When the B data is 0, the switch circuit 7 is turned off at the rise of the count clock CK, and when the LSB data is 1, it is turned off at the fall of the count clock CK.

As a result, an analog value equivalent to ILSB is obtained, and even though the lower bit counter 12 is counting 5 bits of data from 2SB to 6SB, the 6 bit counter is used to count 6 bits of data from LSB to 6SB. It is possible to obtain an analog value equivalent to counting the data of .

That is, in the integral type D/A converter, one clock of the output clock CK corresponds to the analog voltage frame of the ILSB. For example, if the analog voltage of the ILSB in the case of 13 bits is V+ (V+ -4°τ./Cτ.: count period, C: capacitance of the integrating capacitor) as shown in the 4th doujin, the count When the frequency of the clock CK is doubled to 14 bits, the analog voltage of the ILSB is 'A V + ', as shown in Figure 4B.
becomes.

For 13-bit data, if the integration is completed in synchronization with the rise and fall of the count clock CK according to the LSB data, as shown in Figure 5A, the integration will be completed at the rise of the count clock CK. The level difference between the case where the integration is ended synchronously and the case where the integration is ended in synchronization with the falling edge of the count clock CK as shown in FIG. 5B is 'A V + . Therefore, if the timing at which the integration ends is different by the amount of the two count clocks in accordance with the LSB data, an analog voltage frame equivalent to doubling the frequency of the count clock CK will be obtained.

In this example, the current a! The timing at which the switch circuit 7 that controls the switch circuit 8 is turned off is controlled according to the LSB. Therefore, the analog value output from the output terminal 4 has a resolution corresponding to 14-bit digital data.

However, since the lower bit counter 12 is constituted by a 5-bit counter circuit, there is no need to double the frequency of the count clock CK, and the ratio of the current sources can be set as To/i-=2'= Can be set to 32.

Note that the present invention can be similarly applied to a D/A converter configured to perform integration corresponding to the count number of input data using one current source without dividing input data into upper bits and lower bits.

〔Effect of the invention〕

According to this invention, conversion accuracy equivalent to the desired conversion accuracy can be obtained with hardware that is 1 bit less than the hardware required for the desired conversion accuracy of input digital data. The frequency can be lowered, and the ratio of the current values of the current sources of the integrator can be set smaller.

In other words, the digital audio signal with a sampling frequency of 44.1 KHz and a quantization bit number of 14 bits is
When a conventional D/A converter is used, the ratio of the frequency of the count clock and the current source required when performing A conversion is as follows.

On the other hand, according to the present invention, conversion with the same resolution as 14-bit conversion can be realized with 13-bit hardware, and the frequency of the count clock and the ratio of the current sources can be set as follows.

Also, since the count frequency can be lowered in this way, C
- It is possible to have an MO3 configuration, and power consumption can be reduced.

[Brief explanation of drawings]

Figure 1 is a connection diagram of one embodiment of this invention, Figures 2 and 3.
The figure is a waveform diagram used to explain the operation of an embodiment of the present invention, Figures 4 and 5 are waveform diagrams used to explain the embodiment of the invention, and Figure 6 is an example of a conventional D/A converter. FIG. 7 is a waveform diagram used to explain an example of a conventional D/A converter, and FIG. 8 is a connection diagram of another example of a conventional D/A converter. Explanation of main symbols in the drawings 1: Operational amplifier, 2: Integrating capacitor, 4: Output terminal, 5, 7: Current source switch circuit, 6.8: Current source,
11: Upper bit counter, 12: Lower bit counter, 13: LSB data input terminal. Agent Patent Attorney Masatoshi Sugiura<-〇〇-! and (, lo-cL < ω Q Tomisen Nikkeito
1 day/month rA Figure 4 A Figure 4 B Figure 5 A Figure 5 B Conventional 9mukombeta 1 ita 11 Figure 6 too tol t02 neL*n"I entered the corner"% r I'1 Figure 7

Claims (1)

[Claims] In an integrating type D/A converter, two control signals with different timings of 1/2 cycle of the count clock are generated for the current switch that controls the current source of the integrator, and the data of the least significant bit of the input digital data is generated. The D/A converter is characterized in that one of the two control signals is selected in accordance with the above, and the current switch is turned off at the timing of the selected control signal.