JPS62106623A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62106623A JPS62106623A JP24735185A JP24735185A JPS62106623A JP S62106623 A JPS62106623 A JP S62106623A JP 24735185 A JP24735185 A JP 24735185A JP 24735185 A JP24735185 A JP 24735185A JP S62106623 A JPS62106623 A JP S62106623A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- metallic film
- evaporation
- semiconductor substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、リフトオフ法を用いて電極を形成する半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device in which electrodes are formed using a lift-off method.
第2図(よ従来の蒸着法を用いて形成した多層金属膜か
らなる電極の断面図で、1は半導体基板、2は電極パタ
ーンを形成した樹III層、3は第1の金属膜、4は第
2の金属膜、5は前記樹脂M2上の第1の金属膜、6は
同じ(第2の金属膜を示す。FIG. 2 is a cross-sectional view of an electrode made of a multilayer metal film formed using a conventional vapor deposition method, in which 1 is a semiconductor substrate, 2 is a tree III layer on which an electrode pattern is formed, 3 is a first metal film, and 4 is the second metal film, 5 is the first metal film on the resin M2, and 6 is the same (indicates the second metal film).
従来の蒸着法を用いて形成する多層金属膜からなる電極
は、第2図に示すように第1の金属膜3と第2の金属膜
4を真空蒸着法で形成する時、それぞれの金属膜3,4
の蒸着源が異なるため、蒸着ビームの方向が矢印Aおよ
びBのように異なる。In an electrode made of a multilayer metal film formed using a conventional vapor deposition method, when a first metal film 3 and a second metal film 4 are formed using a vacuum vapor deposition method, each metal film is 3,4
Since the evaporation sources are different, the directions of the evaporation beams are different as shown by arrows A and B.
したがって第1の金属膜3を蒸着した後、第2の金属膜
4を蒸着すると、第2の金属膜4は第1の金属膜3の位
置からずれて一部が半導体基板1の表面に付着して形成
される。Therefore, when the second metal film 4 is deposited after the first metal film 3 is deposited, the second metal film 4 is shifted from the position of the first metal film 3 and a part of the second metal film 4 adheres to the surface of the semiconductor substrate 1. It is formed by
従来のリフトオフ法を用いて形成される多層金属膜から
なる電極は、以上のように第2の金属膜4が半導体基板
1の表面に付着しているため、第1の金属膜3のみによ
る電極性能が得られないので、シヲットキー電極では、
熱処理後の削正の劣化等の経時変化が発生する等の問題
点があった。The electrode made of a multilayer metal film formed using the conventional lift-off method has the second metal film 4 attached to the surface of the semiconductor substrate 1 as described above, so the electrode is made of only the first metal film 3. performance cannot be obtained, so with Schottky electrode,
There were problems such as changes over time such as deterioration of the cutting after heat treatment.
この発明は、上記のような間(頂点を解消するためにな
されたもので、第1の金属膜のみによる電極性能が得ら
れる多JΔ金属膜を有する半導体装置の製造方法を得る
ことを目的とする。This invention was made to eliminate the above-mentioned gap (vertex), and an object of the present invention is to obtain a method for manufacturing a semiconductor device having a multi-JΔ metal film that can obtain electrode performance only with the first metal film. do.
この発明に係る半導体装置の製造方法は、半導体基板上
に多層金属膜からなる電極を真空蒸着法で形成ずろ時、
蒸発源からの蒸発ビームを半導体基板上にバターニング
された樹脂層をマスクとして斜め方向からの蒸発ビーム
により第1の金属膜を形成する工程と、前記第1の金属
膜の上に前記゛1つ導体基板に対して垂直方向からの蒸
着ビームに、Lり前記第1の金属膜より小さい面積の第
2の金属片9を形成する工程とによ’) 、+’iil
記半導体基板上に所要数の多層金属膜を形成するように
しtコものである。The method for manufacturing a semiconductor device according to the present invention includes forming an electrode made of a multilayer metal film on a semiconductor substrate by a vacuum evaporation method;
forming a first metal film using an evaporation beam from an evaporation source from an oblique direction using a patterned resin layer on a semiconductor substrate as a mask; A step of forming a second metal piece 9 having a smaller area than the first metal film by applying a vapor deposition beam from a direction perpendicular to the conductor substrate.
A required number of multilayer metal films are formed on the semiconductor substrate.
この発明においては、第1の金属膜の上にこの第1の金
属膜より面積の小さい第2の金属膜が形成され、第2の
金属膜が半導体基板上に付着することなく、電極性能は
第1の金属膜によって得られる。In this invention, a second metal film having a smaller area than the first metal film is formed on the first metal film, and the electrode performance is improved without the second metal film adhering to the semiconductor substrate. Obtained by the first metal film.
第1図はこの発明の一実施例による蒸着法・r用いて形
成した多層金属膜、例丸ば2層の金属膜からなる電極の
断面図である。第り図において、第2図と同一符号は同
じ部分を示す、。FIG. 1 is a cross-sectional view of an electrode made of a multilayer metal film, for example a two-layer round metal film, formed using a vapor deposition method according to an embodiment of the present invention. In Figure 2, the same symbols as in Figure 2 indicate the same parts.
以下、第1図の多層金属膜の形成方法について説明する
。第1図の第1の金属膜7を蒸着する時、蒸着ビームの
方向が、矢印CおよびDの方向を持つように蒸着源を移
動ずろか、あるいは蒸着源全複数箇所に固定して蒸着を
行う。あるいは1箇所の固定蒸着源からの蒸着ビームが
半導体基板1に対し、矢印CおよびDの方向を持つよう
に、半導体基板1を移動しながら蒸着を行う、1以上の
方法により、オーバハング状に形成された樹脂層2の上
端部の電極パターン部分より大きい面積の第1の金属膜
7が半導体基板1上に形成される。次いで、半導体基板
1の表面に矢印Eで示す垂直な蒸着ビームの方向を持つ
蒸着源を用いて、第2の金属膜8の蒸着を行い、第1の
金属膜7の上のみに第2の金属膜8を形成する。A method for forming the multilayer metal film shown in FIG. 1 will be described below. When depositing the first metal film 7 in FIG. 1, the deposition source may be moved so that the direction of the deposition beam is in the direction of arrows C and D, or the deposition source may be fixed at multiple locations. conduct. Alternatively, an overhanging shape may be formed by one or more methods in which vapor deposition is performed while moving the semiconductor substrate 1 so that the vapor deposition beam from one fixed vapor deposition source has the directions of arrows C and D with respect to the semiconductor substrate 1. A first metal film 7 having an area larger than the electrode pattern portion at the upper end of the resin layer 2 is formed on the semiconductor substrate 1. Next, a second metal film 8 is deposited on the surface of the semiconductor substrate 1 using an evaporation source whose evaporation beam direction is perpendicular to the arrow E, and the second metal film 8 is deposited only on the first metal film 7. A metal film 8 is formed.
なお、第1の金属膜7および第2の金属膜8は共に蒸着
源を半導体基板1の垂直方向にセットシて蒸着した場合
、蒸着ビームが理想的な垂直ビームであれば、第2の金
属膜8(よ半導体基板1上に接触しない。しかし、この
方法では第1の金属膜7と第2の金属膜8の大きさが同
一になるため、第2の金属膜8の蒸着源と半導体基板1
の相対的な位置を第1の金属膜7の時と同一にしなけれ
ばならない。現在の装置では、蒸着源と半導体基板1の
相対位置を変更して、第1の金属膜7と第2の金属膜8
を精度よく同一方向から蒸着することは不可能に近い。Note that when both the first metal film 7 and the second metal film 8 are deposited with the deposition source set in the vertical direction of the semiconductor substrate 1, if the deposition beam is an ideal vertical beam, the second metal film 8 (not in contact with the semiconductor substrate 1. However, in this method, the first metal film 7 and the second metal film 8 have the same size, so the evaporation source of the second metal film 8 and the semiconductor substrate 1
The relative position of the metal film 7 must be the same as that of the first metal film 7. In the current apparatus, the relative positions of the evaporation source and the semiconductor substrate 1 are changed, and the first metal film 7 and the second metal film 8 are separated.
It is nearly impossible to deposit from the same direction with high precision.
したがって、この発明では、より自由度を広げろため、
第1の金属膜7を第2の金属膜8より太き(形成する&
着方法とした。また第1の金属膜7は2回に分けて蒸着
するのではなく、連続した工程において形成される。Therefore, in this invention, in order to further expand the degree of freedom,
The first metal film 7 is made thicker than the second metal film 8 (formed &
How to wear it. Furthermore, the first metal film 7 is not deposited in two steps, but is formed in a continuous process.
以上の方法を用いることにより、第2の金属膜8が半導
体基板1表面に付着することがないため、第1の金属膜
7のみによる電極性能を得ることができる。したがって
、上記の方法や用いて、多層金属膜からなろンヨットキ
ー電極を形成すると、熱処理後の削正劣化が少なくなり
信頼性が増す。By using the above method, the second metal film 8 is not attached to the surface of the semiconductor substrate 1, so that electrode performance can be obtained only by the first metal film 7. Therefore, when a Naronyotto key electrode is formed from a multilayer metal film using the method described above, deterioration due to cutting after heat treatment is reduced and reliability is increased.
またオーミック電極においては、コノクク)・抵抗率が
低丁する。Ohmic electrodes also have low resistivity.
なお、上記実施例では多層金属膜として第1゜第2の2
層の金属膜7,8の形成方法について説明したが、リフ
トオフが可能であれば、蒸着源と半導体基板がなす角度
を徐々に垂直に近づけることにより3層以上の多層金属
膜の形成も可能である。Note that in the above embodiment, the multilayer metal film consists of the first and second layers.
Although the method for forming the metal films 7 and 8 in layers has been described, if lift-off is possible, it is also possible to form a multilayer metal film with three or more layers by gradually making the angle between the evaporation source and the semiconductor substrate closer to perpendicular. be.
この発明は以上説明したとおり、半導体基板面に対し、
斜め方向から蒸着して第1の金属膜を形成1ノ、この第
1の金属膜上に前記第1の金属膜より小さい第2の金属
膜を垂直方向から蒸着して順次多層の金属膜を形成する
ようにしたので、第1層目の金1i4膜上のみに第2層
目以降の金属膜が形成できることから、第2層目以降の
金属膜が半導体基板に付着ずろことがなくなるので、性
能の向上した電極を有する半導体装置が得られる効果が
ある。As explained above, in this invention, on the semiconductor substrate surface,
A first metal film is formed by evaporating from an oblique direction. 1) A second metal film smaller than the first metal film is evaporated from a perpendicular direction on the first metal film to sequentially form a multilayer metal film. Since the second and subsequent metal films can be formed only on the first layer of gold 1i4 film, there is no possibility that the second and subsequent metal films will adhere to the semiconductor substrate. There is an effect that a semiconductor device having an electrode with improved performance can be obtained.
第1図はこの発明の一実施例に上る半導体装置の電極形
成方法を示す図、第2図は従来の半導体装置の電極形成
方法を示す図である。
図において、1は半導体基板、2は電極パターンを形成
した樹脂層、7は第1の金属膜、8は第2の金属膜であ
る。
なお、各図中の同一符号は同一・または相当部分を示す
。
代理人 大 岩 増 雄 (外2名)第1図
8第2の嚢凋膜FIG. 1 is a diagram showing a method for forming electrodes in a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional method for forming electrodes in a semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a resin layer on which an electrode pattern is formed, 7 is a first metal film, and 8 is a second metal film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 8 Second capsular membrane
Claims (1)
マスクとして、前記半導体基板上に蒸発源からの斜め方
向からの蒸着ビームにより第1の金属膜を形成する工程
と、その後、前記第1の金属膜の上に半導体基板に対し
て垂直方向からの蒸着ビームにより前記第1の金属膜よ
り小さい面積の第2の金属膜を形成する工程とにより前
記半導体基板上に所要数の多層金属膜を形成することを
特徴とする半導体装置の製造方法。a step of forming a first metal film on the semiconductor substrate by an evaporation beam from an evaporation source in an oblique direction using a resin layer formed with a desired electrode pattern on the semiconductor substrate as a mask; forming a second metal film having a smaller area than the first metal film on the metal film using a vapor deposition beam from a direction perpendicular to the semiconductor substrate, thereby forming a required number of multilayer metal films on the semiconductor substrate; 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24735185A JPS62106623A (en) | 1985-11-05 | 1985-11-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24735185A JPS62106623A (en) | 1985-11-05 | 1985-11-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62106623A true JPS62106623A (en) | 1987-05-18 |
Family
ID=17162117
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24735185A Pending JPS62106623A (en) | 1985-11-05 | 1985-11-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62106623A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02122632A (en) * | 1988-11-01 | 1990-05-10 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
-
1985
- 1985-11-05 JP JP24735185A patent/JPS62106623A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02122632A (en) * | 1988-11-01 | 1990-05-10 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
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