JPS61264739A - Forming method of electrode wiring pattern - Google Patents

Abstract

PURPOSE:To obtain ultrafine wirings capable of being patterned and of high reliability without stepwise disconnection by accumulating an electrode metal by a bias sputtering method while a resin remains after opening a contacting or through hole to flatten a superhigh LSI device. CONSTITUTION:An electrode 10 is deposited by sputtering on a resist 5 by a sputtering device. In this case, a semiconductor substrate 26 is first held on a substrate holder 25, contained in a sputtering chamber 20, and an RF (ratio frequency) bias voltage is applied from an RF power source 28 through an RF matching unit 27. DC power is applied from a DC power source 21 to a target 22 in the chamber 20 to deposit by sputtering the electrode 10. When the substrate bias value is optimized, the shoulder of the contacting hole is etched from a metal coating shape 31 at zero biasing time to a metal shape 32 at bias applying time, thereby completely burying an electrode metal 10a in the hole.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of forming an electrode wiring pattern in which contact holes are completely filled with metal.

(Prior art) Methods for forming electrode wiring patterns include: (i) Depositing electrode wiring material by sputtering or vapor deposition, and then forming wiring by photolithography and etching; C) Depositing wiring material on a resist pattern. A lift-off method in which a wiring pattern is formed by removing the resist after vapor deposition.

and so on.

Since this invention, which will be described later, relates to the latter lift-off method, the lift-off method will be explained when explaining the conventional technology. FIG. 4 is a cross-sectional view showing the procedure for forming wiring by the conventional lift-off method.

First, as shown in No. 411(a), base diffusion 2 and emitter diffusion 3 are performed in the St substrate l, and after forming an insulating film 4 on the upper surface thereof, a resist 5 is applied on this insulating film 4, Base contact 6 and emitter contact 7 are formed by photolithography. Next, holes are made in the insulating film 4 using the resist 5 as a mask.

Next, as shown in FIG. 4(b), an electrode material such as Ti8 is deposited by electron beam evaporation with the resist 5 left in place. Then, when the resist 5 is removed by ultrasonication, Ti8m remains only on the contact 6.7, as shown in FIG. 4(c).

Subsequently, as shown in FIG. 4(d), M9 is deposited as a wiring material by sputtering, and a wiring pattern is formed by ordinary photolithography. Finally, a protective film is formed to complete the device (not shown).

In this method of forming an electrode wiring pattern using the conventional lift-off method, it is important to create a structure that allows the resist pattern to be easily removed using acetone. It must be discontinuous.

As a method of intentionally making the discontinuity, the edge of the resist 5 or the insulating film 4 shown in FIG. When the contact diameter is W, the aspect ratio is H/v21. The thickness of the electrode film deposited on the structure of FIG. 5 or 6 had to be less than half of H.

(Problems to be Solved by the Invention) As described above, since the electrode film 8 is made to overhang on the contact, the electrode film 8a that is cut off on the contact hole is shown in FIG. As shown in the figure, there is a drawback that the deposit is often not deposited over the entire surface of the contact hole.

Further, for the reasons mentioned above, the electrode film thickness cannot be made thicker, and processes such as tapering the resist edge are complicated to create a structure for lift-off.

This invention solves the problems of the above-mentioned prior art.
The present invention provides a method for forming an electrode wiring pattern that solves the problems that the electrode film cannot be deposited on the entire surface of the contact hole, that the electrode film cannot be thickened, and that the process is complicated.

(Means for Solving the Problems) In the method for forming a line electrode wiring pattern of the present invention, a step is introduced in which a resist is left after opening a contact or a through hole, and an electrode metal is deposited by bias sputtering.

(Function) According to the present invention, since the above steps are introduced into the method for forming an electrode wiring pattern, the electrode metal is deposited by bias sputtering after contact photolithography and completely fills the contact hole, thus solving the above problem. Points can be removed.

(Example) Hereinafter, an example of the method for forming an electrode wiring pattern of the present invention will be described based on the drawings. FIG. 1 is a process explanatory diagram of one embodiment. In this 11th part, the same parts as in FIGS. 4 to 6 will be described with the same reference numerals.

First, as shown in FIG. 1(a), in the same way as before,
After forming the St substrate 1, a base diffusion layer, and an emitter diffusion layer (all not shown) and forming an insulating film 4 on the upper surface, a resist 5 is applied, and a base diffusion layer is formed corresponding to the paste diffusion layer and emitter diffusion layer. Contacts and emitter contacts are formed photolithographically. The steps up to this point are the same as conventional ones.

Next, an electrode 10 is sputter-deposited on the resist 5 using the sputtering apparatus shown in FIG. At this time, first, the semiconductor substrate 26 (numerals 1 to 1 in FIG. 1(a)) is placed on the substrate holder 25.
A substrate (indicated by 5) is held and housed in a sputtering chamber 20, and an RF (high frequency) bias voltage is applied from an RF power source 28 via an RF matcher 27. Further, the target 22 in the sputtering chamber 20 is connected to a DC power source 21.
The electrode 10 is sputter-deposited by applying C (direct current) power.

In this case, the substrate bias electrode 10 (Ti-1,5XS
i) Sputter deposit. When the substrate bias value is optimized, the shoulder part of the contact hole becomes as shown in Figure 3.
The metal coating shape 31 at the time of 0 bias is etched as shown by the metal shape 32 at the time of bias application, and the connection between the electrode metal loa in the contact hole and the metal 10 in other areas is broken. As a result, the electrode metal 10a is completely embedded in the contact hole.

Next, as shown in FIG. 1(b), unnecessary metal 10 other than the contact hole is removed by ultrasonic acetone, and then wiring metal 11 is deposited and patterned. For example, when using M-1,5%St as the electrode metal IO, the bias sputtering conditions are as follows:
KW, substrate 26 K 1.5 plots applied and %Ar gas 23
After sputter deposition for 15 minutes at a pressure of 51L11 Torr, a step of -9t-1μm was filled with A/-81c.
In addition, good results can be obtained without discontinuities in the shoulder area. Note that 24 in FIG. 2 is a vacuum evacuation system.

(Effects of the Invention) As described above in detail, according to the present invention, after contact photolithography, a bias sputtering method is used to completely fill the contact hole with electrode metal, and at the same time, a cut is made to facilitate lift-off. Therefore, a VLSI device having a steep step can be made flat. As a result, even in the case of multilayer wiring, fine wiring patterning is possible and highly reliable wiring without step cutting can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are process explanatory diagrams of an embodiment of the method for forming an electrode wiring pattern of the present invention, and FIG. 2 is a bias sputtering apparatus applied to the method for forming the same electrode wiring pattern. 3 is a cross-sectional view showing the metal coating shape obtained by applying the bias sputtering method to the method of forming the electrode wiring pattern, and FIG. 4 (a)
) to 4(d) are process explanatory diagrams of a conventional method for forming an electrode wiring pattern, and FIGS. 5 and 6 are cross-sectional views of a structure for lift-off using photolithography in the conventional method for forming an electrode wiring pattern, respectively. It is. l... SL substrate, 4... Insulating film, 5... Resist, 10... Electrode, lOa... Electrode metal, 11...
・Wiring metal, 20...Sputter chamber, 22...
- Target, 25...substrate holder, 26... substrate. 5 Lugist 10: f pole Figure 2

Claims (2)

[Claims] (1) After forming an insulating film on a semiconductor substrate, applying a resist and forming a through hole or contact hole by photolithography, and after forming the through hole or contact hole, bias sputtering with the resist remaining. A method for forming an electrode wiring pattern, comprising the step of filling the through hole or contact hole with an electrode metal. (2) Conditions for bias sputtering are: the dope rate at 0 bias is A, the dope rate at bias application is B, and DC power is applied to the target so that (A-B)/A is 20% or more. 2. The method of forming an electrode wiring pattern according to claim 1, wherein the vapor deposition is performed while applying a high frequency bias to the substrate.