JPS62106496A - Composite video signal generation circuit using graphic display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a composite video signal generation circuit for NTSC using a graphic display controller.

(Prior art) Graphic display controller using conventional technology) o-
As a composite video signal generation circuit using A method is known in which data is output from a frame memory based on an output clock to generate a composite video signal.

For example, FIG. 2 is a block diagram showing an example of a conventional NTSC video signal generation circuit. Second
In the figure, 201 is a transistor, 2Q2.212.2
22 are AND gates, 203 are PLL circuits, 2
04 is a VCo, and 205 is a vertical synchronization generation circuit.

In FIG. 2, an NTSC composite synchronization signal input to a signal line 211 is buffered via a transistor 201 and then input to a vertical synchronization generation circuit 205 via an A, ND gate (202).

External vertical synchronization is output from the vertical synchronization generation circuit 205 to the signal line 213 according to the input synchronization signal.

On the other hand, the composite synchronization signal output from the AND gate 202 is input to the PLL circuit 203 except for the vertical synchronization period. This inhibition is implemented by AND gates 212 and 222. The PLL circuit 203 includes a phase detector, a charge pump, an active low-pass filter amplifier, etc., and detects the difference between the horizontal synchronization signal taken out from the transistor 201 and the horizontal synchronization signal output from the graph ink display controller. The oscillation frequency of the VCO 204 is controlled by driving a charge pump and using the charge of a filter consisting of an external resistor and an external capacitor.

(Problems to be Solved by the Invention) In the composite video signal generation circuit using the conventional graphic display controller described above, the reference clock is PL.
Since this taro clock is output from the L circuit and is used exclusively for the graphic display controller, there is a drawback that the clock does not reach the specified value until synchronization is achieved, causing the image to overlap. Furthermore, because the color signal to be supplied to the color encoder and the clock to be supplied to the graphic display controller are not integral multiples, the phases of the synchronization signal/luminance signal and color burst signal in the composite video signal do not match. It has the disadvantage that color shift may occur or no coloring may occur.

The object of the present invention is to provide an original oscillator with a frequency that is the least common multiple of a graphic display controller clock and an NTSC synchronous number generator clock, generate each clock and color subcarrier signal from the original oscillator by a frequency dividing circuit, Graphic display controller &
To provide a composite video signal generation circuit using a graphic display controller configured to eliminate the above drawbacks and establish stable synchronization by operating as a slave to an NTSC synchronization signal generation circuit. be.

(Means for Solving the Problems) A composite video signal generation circuit using a graphic display controller according to the present invention includes a reference clock generation means, a graphic display controller, a CPU, a frame memory, an image control means, and an NTSC.
The apparatus includes a C synchronization signal generator, a first field drive signal detector, and a color encoder.

The reference clock generation means is provided with a nuclear power generator (iron generator) and a plurality of frequency dividing circuits and is used to generate a reference clock.

The graphic display controller is for generating the reference tally clock generated by the reference clock generating means.

The CPU is responsible for controlling the graphics display controller.

The frame memory is controlled by a graphics display controller and is for storing digital image information.

The image control means is for converting digital image information output from the frame memory into an RGB video signal.

The NTSC synchronization signal generator operates based on a reference clock and is used to generate an NTSC synchronization signal.

The first field drive signal detector detects the first field drive signal of the synchronization signal.
This is for detecting field drive signals.

The color encoder is for generating a composite sync signal using an RGB video signal, a composite sync signal output by a sync signal generator, and a reference clock.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a composite video signal generation circuit using a graphic display controller according to the present invention. In Figure 1, l is the original oscillator,
3 is the first frequency divider circuit, 5-digit second frequency divider circuit, 7 is the eighth frequency divider circuit, 9 is the NTSC synchronization signal generator, and lO is the fourth frequency divider circuit.
12 is a graphic display controller, 13 is a CPU, Is is a frame memory, 16 is a parallel/serial converter, 18 is a digital/analog converter, 20 is a color encoder, 23 is a first field drive signal detector It is.

In FIG. 1, the original oscillator 1 generates six new tarlocks on the signal line 2 at frequencies that are the greatest common multiple of the graphic display controller clock, the NTSC synchronization signal generator clock, and the color subcarrier signal. . The first frequency dividing circuit 3 makes the output of the original oscillator 1 115, and sends it onto the signal line 4 as a dot clock. This signal outputs the output data of the frame memory 15 in parallel/
Parallel/serial converter 16 for serial conversion
supplied to At the same time, the shift clock on the signal line 4 is also supplied to the second frequency divider circuit 5, whereby the second frequency divider circuit 5 generates a clock for the graphic display controller on the driver 6.

On the other hand, the clock on the signal line 2 is also input to the third frequency divider circuit 7, frequency-divided into 1/4, and supplied as a dot clock from the signal line 8 to the NTSC synchronization signal generator 9. The dot clock on the signal line 8 is frequency-divided to 1/4 by the fourth frequency dividing circuit 1o, and is supplied to the color encoder 20 from the signal line 11 as a color subcarrier signal.

The graphic display controller 12 is the CPU 1
3, the slave mode is set, and synchronization is established with the pNTSC synchronization signal generator 9 by the first field drive signal on the signal line 14. The graphic display controller 12 reads data from the frame memory 15 under the control of the CPU 13 and sends it to the parallel/clear converter 16. Based on the shift clock on signal line 4, the above data is transferred to signal 817 as serial data.
is input to the digital/analog converter 18 and supplied to the color encoder 20 as an RGB video signal via the signal line 19. At this time, the RGB video signal, that is, the serial data output on the signal line 19, is transmitted between the graphic display controller 12 and the NTS
Due to the synchronization relationship with the C synchronization signal generator 9, it is in a state of synchronization with the horizontal/vertical synchronization signal.

The NTSC synchronization signal generator 9 generates a composite synchronization signal (on the signal line 21) based on the dot clock on the signal line 8, the first
A field drive signal (on signal line 14), a second field drive signal (not shown), etc. are output. The composite synchronization signal on signal line 21 is supplied to color encoder 20 to generate a composite video signal.

On the other hand, in order for the graphic display controller 112 to operate in slave mode, only the first field drive signal on the signal line 14 is required;
The field drive signal output from the SC synchronization signal generator 9 onto the signal line 22 is input to the first field drive signal detector 23. The first field drive signal detector 23 detects a predetermined signal and supplies it to the graphic display controller 12. The color encoder 20 receives RGB video signals (
A composite video signal is generated on the signal line 24 based on the composite synchronization signal (on the signal line 21), and the color subcarrier signal (on the signal line ll), and the composite video signal is output to the output terminal 2.
Output from 5 to the outside.

(Effects of the Invention) As explained above, the present invention provides a single clock source for the graphic display controller, the NTSC synchronization signal generator, and the color subcarrier signal. , horizontal/
It is possible to establish synchronization between the vertical synchronization signal and the color subcarrier signal from the beginning of system initialization, and there is an effect that disturbances in the displayed image and color shift can be prevented until synchronization is achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a composite video signal generation circuit using a graphic display controller according to the present invention. FIG. 2 is a block diagram showing an example of a composite video signal generation circuit of a graphic display controller according to the prior art. l...Original oscillator 3.5.7,10Φ/Φ frequency dividing circuit 9...NTSC synchronization signal generator 12...Graphic display controller 13...CPU 15...Frame memory 16--- Parallel/serial converter 18... Digital/analog converter aυ 1st 20... Color encoder 23 Ken... 1st field drive signal detector 24...
・Output terminal

Claims (1)

[Claims] a reference clock generating means for generating a reference clock including an original oscillator and a plurality of frequency dividing circuits; a graphic display controller for generating the reference clock generated by the reference clock generating means; and the graphic display. a CPU for controlling the controller; a frame memory controlled by the graphic display controller for storing digital image information; and a frame memory for converting the digital image information output from the frame memory into an RGB video signal. an NTSC synchronization signal generator operated by the reference clock to generate an NTSC synchronization signal, and a first field drive for detecting a first field drive signal of the synchronization signal. a signal detector and the RGB video signal;
a composite synchronization signal output by the synchronization signal generator;
and a color encoder for generating a composite video signal using the reference clock. A composite video signal generation circuit using a graphic display controller.