JPS6210588Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital timer circuit for a combustion controller that can set timing output arbitrarily and achieve a fail-safe circuit configuration.

Recently, digital timers or digital logic circuits have been housed in a single integrated circuit element and have begun to be commercially available as dedicated chips for combustion control for gas or oil. The advantage of developing this type of dedicated chip is that if only the basic sequence operations common to gas combustors, oil combustors, and combustors of various combustion capacities are made into dedicated elements,
This is because by only slightly considering things outside the integrated element, the design becomes significantly easier than designing a control device according to a conventional combustor, and it is possible to provide versatility.

However, due to this need for versatility, a digital timer circuit can obtain any timing output, and even if a conduction or open failure occurs in each element that makes up the timer circuit, this timing time will not change. There is a need to prevent this from happening.

However, as shown in FIG. 1, the timer circuit in the conventional integrated control element has a plurality of terminals exposed outside the integrated chip, for example three terminals a ₁ , a ₂ and a ₃ .
By giving a signal of "0" or "1" to each terminal, a time designation signal is created, which is added to decoder 1, and eight types of time signals T ₁ to T determined by the output of this decoder 1 are generated. Make ₈ and each signal
Divide the clock from the clock pulse generator 3 according to T ₁ to T ₈ and control the number of division stages,
This is to obtain a timing signal output.

However, although this method can secure considerably more timing by increasing the number of terminals a ₁ , a ₂ ...a _o , if a failure occurs in the decoder, a timing completely different from the preset timing will be generated. There is a risk that

For example, in the case of the pre-purge time, if the timing decreases below the predetermined time, there is a risk of explosion and ignition, and in the case of the ignition trial time, conversely, if a failure occurs that takes too long, it will be extremely dangerous. This is dangerous, and if ignition fails during this period, a large amount of gas will fill up.

The present invention provides a digital timer circuit for combustion control that does not have such drawbacks.

In FIG. 2, 10 indicates an integrated element section, and 1
Reference numeral 1 indicates an external circuit, and the integrated element 10 has three time setting terminals 12, 13, and 14, and a capacitor 15 and a resistor 16 are connected between the terminals as shown in the figure, together with an oscillation drive circuit 30. It constitutes an RC oscillation circuit. The drive circuit 30 may be any known circuit, such as any relaxation oscillation drive circuit using two switching transistors or a PUT element. In FIG. 2, it is composed of a first timer circuit for pre-purge timing and a second timer circuit for ignition trial timing. ... ³³ⁿ , and false flame check circuits 34, 34'... ³⁴ⁿ . This prepurge end timing output is stored in a storage circuit 41 provided to an AND gate 40.

On the other hand, the second timer circuit for ignition trial timing is similarly composed of flip-flops 42, 42 ^' , . Incidentally, a case has been disclosed in which the clock is energized by the clock 2 obtained by dividing the power cycle by the second timer circuit.

In such a configuration, first, the signal "0" indicating the start of the first timer circuit is connected to the terminal M.
2. Then, the clock 1 from the oscillation drive circuit 30 is applied to each flip-flop, and in response, the first-stage flip-flop 33 reads "0" from the conductor 32. The check circuit 34 only passes the flip-flop output unless the flame signal=1 becomes "0". In other words, the pseudo flame check circuit 34 is composed of a NOT gate and a NAND gate connected in series, and the signal is "1" when there is no flame and "0" when there is flame.
Therefore, when there is no flame, the signal is "1", so in the pseudo flame check circuit 34, the input of the NOT gate becomes the output of the NAND gate as it is, but when there is flame, the signal is "0", so the NOT The output of the NAND gate is "1" regardless of the input to the gate. Therefore, the clock signal "0" acts as a shift register and advances to the next stage flip-flops 33', 33", . . . as the clock 1 is supplied.
When the output of the final stage flip-flop ³³ⁿ is "0", all the inputs of the AND gate 40 are "1", so "1" is stored in the storage circuit 41, indicating that the pre-purge time has ended.

On the other hand, a timing synchronization circuit consisting of inverters 43 and 43' and a latch circuit 44 is provided between the first timer circuit and the second timer circuit. Therefore, when the last "0" time measurement output of the first timer circuit appears, "1" is stored in the latch 44 via the inverter 43. Normally, clock 1 and clock 2 are not synchronized, so it is temporarily latched here, and clock 2 of the second timer circuit is
A "0" signal is read into the flip-flop 42 with the first signal of , and the latch circuit is simultaneously reset with its clock 2. Thereafter, in the second timer circuit, the "0" clock signal is sequentially shifted in the same way as in the first timer circuit. Note that since the flip-flop outputs of the first and second timer circuits are input to the AND gate 45, the "0" clock signal is
During the timing when the position of either the first or second timer circuit is shifted, one of the inputs of the AND gate 45 is "0", so the output during that period is "0". .

On the other hand, AND gate 47 has AND gate 4
5 is inputted via the inverter 46, and the output of the memory circuit 41 is inputted to the output terminal 20.
It gives timing output to.

That is, as shown in FIG.
Considering the output of 0 and the AND gate 45,
The output of AND gate 47 constitutes a one-shot circuit that delivers a predetermined timing output _T2 .

Note that in this embodiment, the clock signals supplied to the first timer circuit and the second timer circuit are provided by clock 1 and clock 2, respectively, so that only the prepurge time _T1 can be arbitrarily changed. The clock to be supplied to the second timer circuit is not limited to the one obtained by dividing the power supply frequency, but the clock 2 can also be obtained by forming an RC oscillation circuit with an external resistor capacitor as in the first timer circuit. It's okay. Even in this case, if a latch synchronization circuit is used, the clock 1 and clock 2 signals will always be synchronized even if they are unrelated to each other.

As described above, according to the present invention, an RC oscillator circuit is used to configure the clock signal supplied to the combustion control timer circuit at an arbitrary period and in a fail-safe manner, and this resistor capacitor is connected outside the integrated circuit element. Since it is configured to be externally connected, a safe timer circuit can be constructed with certainty. In particular, RC oscillation circuits have the advantage that the oscillation itself disappears if there is a failure in any of the circuit elements, so it is extremely safe and will not cause oscillation at an unexpected frequency.

In addition, since the first timer circuit for ensuring the pre-purge time and the second timer circuit for ensuring the ignition trial time are connected via a timing synchronization circuit, the first timer circuit that is supplied to the first and second timer circuits is , and the second clock signals are always synchronized even if they are unrelated to each other, so that effects such as ensuring accurate timer time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an explanation of the operation of a conventional combustion control timer circuit, FIG. 2 is a circuit connection diagram showing an embodiment of the timer circuit of the present invention, and FIG.
FIG. 3 is a timing diagram showing timing output signals of the timer circuit of the same embodiment. In the figure, 10... combustion control integrated element, 11... external circuit, 15... capacitor, 16... resistor, 30... oscillation drive circuit, 40, 45 and 47... AND gate.

Claims (1)

[Scope of utility model registration request] A first timer circuit for securing a prepurge time in which a plurality of flip-flops and a plurality of pseudo flame check circuits are alternately connected in cascade; and a first clock pulse generation circuit for supplying clock pulses to each of the flip-flops and sequentially shifting the flip-flops. a flame signal supply source for supplying a flame signal to each of the pseudo flame check circuits; a second timer for securing an ignition trial time in which a plurality of flip-flops are connected in cascade; and a clock pulse to each flip-flop of the second timer. A second clock pulse generation circuit that supplies clock pulses to sequentially shift the flip-flops, and a timing synchronization circuit that is connected between the output side of the first timer circuit and the input side of the second timer circuit are simply described. 1. A digital timer circuit for a combustion controller, characterized in that the digital timer circuit is housed in one integrated element, and a resistor and a capacitor constituting the first clock pulse generation circuit are externally attached outside the integrated element.