JP2710476B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for stopping generation of an internal clock by a clock stop signal.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional clock generation circuit includes input protection circuits 1 and 2, an input circuit 8, a clock generation circuit 6, an internal circuit 7, and a NOR circuit E1. Was composed.

Next, the operation will be described.

FIG. 4 is a time chart for explaining the operation of the conventional clock generation circuit shown in FIG.

The clock stop signal ST is an "L" active signal, and is at "H" level during normal operation. The clock stop signal ST is input to the input circuit 8 via the input protection circuit 2. The level is inverted by the input circuit 8 and "
An L-level output signal j is input to the NOR circuit E1. The external clock signal CLK is input as an output k of the NOR circuit E1 to the clock generation circuit 6. An "H" -level output k is a clock generation signal. The internal clock CP is generated by the clock generation circuit 6. The internal clock CP is input to the internal circuit 7 to operate it.

Next, a description will be given of the case of executing the clock stop. In FIG. 5A, the clock stop signal ST is L
At this point, the level changes from the “H” level to the “L” level. Then, the output j of the input circuit 8 is inverted and changes to "H" level. At this time, the NOR circuit E1 stops transmitting the external clock signal CLK and fixes the signal k to the “L” level. As a result, the clock generation signal is interrupted, and the clock generation circuit 6 stops generating the internal clock CP.
Therefore, the operation of the internal circuit 7 also stops.

Next, when releasing the clock stop state, the clock stop signal ST is changed from "L" level to "H" level at the point N as shown in FIG. 5 (B). Then, the output j of the input circuit 8 is inverted and changes to "L" level. At this time, the NOR circuit E1 restarts transmission of the external clock signal CLK, and the output k of the NOR circuit E1 is at the "H" level, that is, the clock generation signal is input to the clock generation circuit 6 as in the normal operation state. Is done. The clock generation signal generates an internal clock CP by the clock generation circuit 6. Internal clock CP
Has been input to the internal circuit 7 to operate it.

[0008]

The above-described conventional clock generation circuit has the following disadvantages: when the input timing is such that the clock stop signal, which is an asynchronous input, is inverted immediately after the external clock signal falls or immediately before the external clock signal rises. There is a drawback that an extremely short time, that is, a spike-like clock generation signal is transmitted as an input to the clock generation circuit and causes a malfunction. Further, when noise is generated in the clock stop signal, the noise is transmitted as a spike-like clock generation signal and becomes an input to the clock generation circuit, thereby causing a malfunction.

[0009]

According to the present invention, there is provided a clock generation circuit which operates in response to supply of an internal clock.
Internal clock generating means for generating the internal clock
A clock generation circuit that generates the internal clock in synchronization with an external clock signal supplied from the outside and stops the internal clock in response to the supply of a clock stop signal from the outside; A shift circuit that sequentially shifts the clock stop signal by a predetermined number of shifts in synchronization with the clock signal and generates an internal clock stop signal that stops the internal clock when the shift of the number of shifts is completed. a latch circuit Ru <br/> to generate a latch signal to latch said internal clock stop signal, the input terminal and the front of the external clock signal
The serial clock is inserted between the internal clock generating means and the
Switch and the internal clock stop signal.
In response to passing the external clock signal respectively.
And a second logic circuit .

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention.

As shown in FIG. 1, the clock generation circuit of this embodiment includes input protection circuits 1 and 2, an input circuit 3 having two stages of inverters, a shift circuit 4, a latch circuit 5,
Clock generation circuit 6, internal circuit 7, input protection circuit 1
NOR circuit E to which the output of the latch circuit 5 and the output of the latch circuit 5 are input.
1, E2 and inverter circuits I1 to I3 connected in series between the NOR circuits E1 and E2.

The shift circuit 4 includes flip-flops 41 to 44, which are RS flip-flops. The shift circuit 4 receives the output of the input circuit 3 and outputs
The output of the R circuit E1 and the inverted signal of the output of the inverter circuit I1 are input as control signals, and the latch circuit 5 is controlled by the output.

The latch circuit 5 receives the output of the input circuit 3 and applies the output to the NOR circuit E1.

The other components are the same as those described in the aforementioned conventional example.

Next, the operation of this embodiment will be described.

FIGS. 2A and 2B are time charts for explaining the operation of the circuit of this embodiment shown in FIG. 1. FIG. 2A shows the operation at the time of executing the clock stop, and FIG. Respectively.

First, the operation at the time of executing the clock stop will be described with reference to FIG.

At the point A, the clock stop signal ST
The output signal a of the input circuit 3 also changes to the “L” level from the “H” level to the “L” level, at which time the shift circuit 4 outputs the output signal g of the NOR circuit E1 and the output signal g of the inverter I1. The flip-flops 41 to 44 operate at the timings B to E of the external clock signal CLK using the inverted signal h as a clock pulse.
Is controlled as follows. At the timing B, the output signal b of the flip-flop 41 is set to the “L” level. At timing C, the output signal c of the flip-flop 42 is set to the “L” level. At timing D, the output signal d of the flip-flop 43 is set to "L" level. At the timing E, the output signal of the flip-flop 44 is set to "L" level, and the output signal e of the shift circuit 4 is set to "H" level. The output signal e of the "H" level shift circuit 4 is NO
R circuit E2 is blocked, input protection circuit 1, NOR circuit E
1. The transmission of the external clock signal CLK input via the inverters I1 to I3 is stopped, and the output signal of the NOR circuit E2, that is, the clock generation signal i is fixed at the "L" level. As a result, the clock generation signal is interrupted, and the clock generation circuit 6 stops generating the internal clock CP.
Therefore, the operation of the internal circuit 7 also stops. At the same time as the output signal e of the shift circuit 4 goes to "H" level, the latch circuit 5 takes in the signal a as an input, changes the output signal f to "H" level, and outputs the output signal g of the NOR circuit E1. At the “L” level.

Next, the operation for releasing the clock stop state will be described with reference to FIG.

To release the clock stop state, the clock stop signal ST is changed from "L" level at point F to "L" level.
H ”level. Then, the output a of the input circuit 2
Is inverted and changes to the “H” level. The output signal f of the latch circuit 5 changes to "L" level. Then, NOR
Circuit E1 transmits external input clock signal CLK as output signal g. At this time, the shift circuit 4 operates using the output signal g of the NOR circuit E1 and its inverted signal h by the inverter I1 as clock pulses, and switches the flip-flops 41 to 44 at the respective timings G to K of the external clock signal CLK. Control is performed as follows. At timing G, the output signal b of the flip-flop 41 is set to the “H” level. At the timing H, the output signal c of the flip-flop 42 is set to the “H” level. At timing I, the output signal d of the flip-flop 43 is set to the “H” level. At the timing K, the output signal of the flip-flop 44 becomes “H” level, and therefore, the output signal e of the shift circuit 4 becomes “H”.
The output signal e of the shift circuit 4 at the "L" level is transmitted to the NOR circuit E2, and the external clock signal CLK input through the input protection circuit 1, the NOR circuit E1, and the inverters I1 to I3. Resumes transmission of N
The output signal of the OR circuit E2, that is, the clock generation signal i is input to the clock generation circuit 6. The clock generation signal is
The clock generation circuit 6 generates the internal clock CP. The internal clock CP is input to the internal circuit 7 to operate it.

[0022]

As described above, the clock generation circuit of the present invention sequentially shifts the clock stop signal by a predetermined number of shifts in synchronization with the external clock signal, and outputs the internal clock stop signal when the shift of this shift number is completed. , And a latch circuit controlled by an output of the shift circuit to latch a clock stop signal, thereby synchronizing the clock stop signal with an external clock signal, thereby transmitting a spike-like clock generation signal. Thus, there is an effect that a malfunction that is performed and malfunctions can be prevented. In addition, even when noise is generated in the clock stop signal, there is an effect that a malfunction that this noise is transmitted as a spike-like clock generation signal and malfunctions can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock generation circuit of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the clock generation circuit according to the embodiment.

FIG. 3 is a block diagram illustrating an example of a conventional clock generation circuit.

FIG. 4 is a time chart showing an example of an operation in a conventional clock generation circuit.

[Explanation of symbols]

 1, 2 input protection circuit 3 input circuit 4 shift circuit 5, 41 to 44 latch circuit 6 clock generation circuit 7 internal circuit E1, E2 NOR circuit I1 to I3 inverter circuit

Claims (2)

(57) [Claims] An operation is performed in response to the supply of an internal clock.
Internal circuit and internal clock for generating the internal clock
A clock generating circuit for generating the internal clock in synchronization with an external clock signal supplied from the outside, and stopping the internal clock in response to the supply of a clock stop signal from the outside; A shift circuit that sequentially shifts the clock stop signal by a predetermined shift number in synchronization with a clock signal and generates an internal clock stop signal that stops the internal clock when the shift of the shift number is completed; and an output of the shift circuit. A latch circuit controlled to latch the internal clock stop signal and generate a latch signal; an input terminal for the external clock signal;
The latch signal and the
The external clock in response to the supply of each of the internal clock stop signals.
First and second logic circuits for passing clock signals respectively
Clock generation circuit characterized by comprising a road. 2. The clock generation circuit according to claim 1, wherein the shift circuit includes the cascade-connected RS flip-flop of the shift number for shifting the clock stop signal using the external clock signal as a clock pulse.