JPH0144927Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a digital combustion control device applied to a gas or oil combustor.

[Conventional technology]

In order to safely ignite a combustor that uses gas or oil as fuel, it is necessary to control devices such as valves and igniters according to a predetermined sequence, and to proceed with the sequence while checking the operation of each device. is desired. . Conventional digital combustion control devices handle these combustor control requirements using simple electrical circuits, such as relay sequence circuits.

[Problem to be solved by the invention]

Conventional digital combustion control devices are configured as described above, so in order to satisfy the fail-safe property of always operating on the safe side even in the event of a failure of the circuit itself, the circuit configuration must become complicated, and the response speed and There are problems with reliability. Under these circumstances, the use of small, inexpensive, and highly reliable integrated circuits is being considered, but in this case, sufficient fail-safety must be taken into account to ensure that no dangerous situation occurs in the event of a sequence circuit failure. It won't happen. However, there is a problem in that fail-safe cannot be ensured if the shut-off means provided to achieve this fail-safe fails.

This idea was made to solve the above problems, and in order to achieve fail-safety, the shut-off means is checked for failure.
The object of the present invention is to obtain a digital combustion control device that ensures failability against failures in digital circuits.

[Means to solve the problem]

The digital combustion control device according to this invention has a first memory M1 which is set when it detects that the shaft-off means is normal when a start signal is given, as shown in the claim correspondence diagram of FIG.
and a prepurge shift register which is activated upon receiving the output when the first memory M1 is set, measures a predetermined prepurge period, and outputs a prepurge end signal at the end of this prepurge period.
PSR, a second memory M2 that is set in response to the pre-purge end signal, and an output signal in the state where the second memory M2 is set, to open the pilot valve and ignite the pilot burner. a drive circuit 6 that operates in response to the prepurge end signal, and a trial shift that starts up in response to the prepurge end signal, measures a predetermined ignition trial period, and outputs an ignition trial end signal at the end of this ignition trial period. A third memory M3 that is set in response to the register TSR and the flame detection signal indicating the ignition of the pilot burner or the trial end signal.
The drive circuit 7 operates to open the main valve and ignite the main burner in response to the output signal when the third memory M3 is set. A gate circuit (NA1,
AN3, NA2, etc.), the shutoff means is a transistor that receives the check signal obtained by reading the start signal at the falling edge of the synchronization pulse and the alarm signal. Q5 and the relay K5 connected to the collector side of this transistor.
and the above transistor Q via this relay K5.
A drive power source (not shown) that applies a pulsed drive voltage synchronized with the synchronization pulse to the collector of No. 5.
and a smoothing circuit (capacitor C2, resistor R2) for extracting an H level output from the collector side of the transistor Q5 when it is off and applying a positive voltage to the collector. .

[Effect]

The shut-off means in this invention is such that when the transistor Q5 is off, the terminal AI is held at H level, but when the transistor Q5 is turned on, the charge in the capacitor C2 forming the smoothing circuit is instantly discharged through the transistor Q5. Therefore, it immediately becomes L at the level of terminal AI.

In other words, when the shutoff means is checked, the charge stored in the capacitor C2 is simply discharged to the transistor Q5, so that the built-in relay K5 will not malfunction. Moreover, if ignition fails during the pilot trial period in the sequence progression process, the input to the base of transistor Q5 does not change and remains conductive, so relay K
5 operates to perform a shut-off operation and achieve fail-safety.

〔Example〕

An embodiment of this invention will be described below with reference to the drawings. In Figure 2, terminal SE has
When a recycle operation is selected, an H level signal is applied, and when a non-recycle operation is selected, an L level signal is applied.

A signal that becomes H level when a heat request occurs is supplied to the terminal TS, and based on this signal, a TS on pulse and a TS off pulse are generated by the converter 1 and the OR circuit OR10.

A signal that becomes H level when the ignition of the pilot burner is detected is supplied to the terminal FD, and the converter 2 converts the film (FD) based on the roller signal.
An on-pulse and a flame-off pulse are created.

A synchronizing pulse Φ1 of an appropriate frequency (eg, power supply frequency) is applied to the terminal Φ1.

A connection point between a resistor R1 and a capacitor C1 connected in series, which constitute a time constant circuit, is connected to the terminal CK, and a pulse with a frequency corresponding to the time constant is transmitted from an oscillator 3 connected to the terminal CK to a frequency divider 4. is supplied to Further, the output side of an AND circuit AN11 which receives the Q output of the memory M1 and the output of the memory M2, which will be described later, is connected to the terminal CK via a resistor R3. Therefore, the AND circuit
The time constant of the time constant circuit changes between when the output of AN11 is at H level and when it is at L level, and the oscillator 3 outputs pulses of different frequencies.

Four types of clock pulses T ₀ -T ₃ having a fixed mutual ratio are taken out from an arbitrary frequency division stage of the frequency divider 4. . In this example, it is assumed that when the output of the AND circuit AN11 is at L level, the frequency of the clock pulse T ₀ is 1/6 Hz, and T ₀ =1/16T ₁ .
The pre-purge shift register PSR has multiple stages (5 stages in this example) of D-flip-flops FF1.
-FF5, the Q output of each D-flip-flop is connected to the next-stage D-flip-flop, and the output is connected to an AND circuit AN1. A clock pulse T ₀ is also supplied to the clock input of each D-flip-flop. Similarly to the pre-purge shift register PSR, the trial shift register TSR consists of five stages of D-flip-flops FF6 to FF10.
They differ in that they are controlled by clock pulse _T1 . The Q outputs of the D-flip-flops FF6 to FF9 are input to the AND circuit AN2, and the output thereof is fed to the NAND circuit along with the output of the AND circuit AN1.
Connected to NA1. These shift registers PSR and TSR are clock pulse
The input signal is shifted in synchronization with T ₀ and T ₁ to determine the timing of valve control, which will be described later.

The matching circuit MP consisting of the AND circuits AN12, AN13 and the OR circuit OR7 receives the Q output of the D-flip-flop FF5 at the final stage of the prepurge shift register PSR, and then sequentially operates the trial shift register TSR. Establish the necessary timing.

On the other hand, the terminal AO is connected to the base of a transistor Q5 of an external circuit constituting the shutoff means, and a relay K5 is connected as a collector load of the transistor Q5. The other end of the relay K5 is connected to a drive power source (not shown) for supplying a drive current obtained by half-wave rectifying alternating current at the power supply frequency. .

Therefore, when transistor Q5 is turned on, relay K5 is activated and the circuit power is immediately cut off. The collector of the transistor Q5 is connected to the terminal AI via a smoothing circuit consisting of a resistor R2 and a capacitor C2, in parallel with the resistor R2, and in a forward direction with respect to the collector-emitter junction of the transistor Q5. A diode D1 is connected.

Therefore, when transistor Q5 is off, terminal AI is held at H level, but when transistor Q5 is turned on, the charge in capacitor C2 is transferred to diode D1 and transistor Q5.
Since the voltage is instantly discharged through the terminal, the level of the terminal AI becomes L immediately.

Terminals V1, IG, and V2 are connected to the bases of transistors Q2, Q3, and Q4, respectively. These transistors Q2, Q3, and Q4 are switching elements for controlling a pilot valve control relay K2, an igniter control relay K3, and a main valve control relay K4, respectively.

Further, the terminal AI connected to each collector side of the transistor Q5 is used to take out a signal indicating that the transistor Q5 is operating normally when its level changes from H to L. Figure 3 shows each contact K2- of relays K2, K3, and K4.
1, K3-1, K4-1, and Akastat TH, which is turned on when a heat request occurs, shows an example of the connections between fan motor M, pilot valve PV, igniter IG, and main valve MV.

This configuration generates heat demands and reduces the
When TH is turned on, the fan motor M for blowing air is first started, and after a predetermined pre-purge period has elapsed, the relay K2 is operated and its contact K2-1 is turned on, and the pilot valve PV is opened. At this time, relay K3 is inactive, and its contact K3
Since contact K2-1 is on the igniter IG side, the igniter IG is also energized at the same time as the contact K2-1 is turned on, and ignition of the pilot burner is attempted.

If pilot burner ignition is detected during a predetermined pilot trial period, relay K3 operates and its contacts K3-1 switch to switch igniter IG.
is deactivated, and when relay K4 is activated and its contact K4-1 is turned on after a predetermined post-ignition period, main valve MV is opened.

Again in Figure 2, TA is the timer that sets the post-ignition period, and TB is the main valve.
This is a timer that sets the MV delay time. Timer TA is activated by the output when memory M3, which will be described later, is set, and timer TB is activated by the output when memory M3, which will be described later, is set.
Starts with the output when TA finishes measuring the set time. And timers TA and TB are memory M3
At the same time, it is reset by a reset signal supplied via the OR circuit OR7.

A clock selection circuit CSE is provided to supply clock signals to these timers TA and TB. This clock selection circuit CSE is composed of AND circuits AN14, AN15, an OR circuit OR8, and an inverter IN3, and has a function of selecting one of clock pulses _T2 and _T3 according to the level of terminal SE.

In FIG. 2, the symbol AN represents an AND circuit, OR represents an OR circuit, NA represents a NAND circuit, IN represents an inverter, and M represents a memory consisting of an RS-flip-flop.

The operation of the combustion control device of this invention constructed in this way will be explained with reference to the time charts shown in FIGS. 4A and 4B. Figure 4A shows the case of an oil combustor, and Figure 4B shows the case of a gas combustor, where a is the pre-purge period, b is the ignition trial period, c is the post-ignition period, and d is the case. represent the delay periods of the main valve MV, respectively.

(Pre-purge operation) Now assume that terminal SE is held at H level by the output of an external sequence selector.
When a heat request occurs in this state and the level of the terminal TS changes from L to H, this H level signal is applied to the input of the NAND circuit NA1 via the AND circuit AN17. Further, since there is no flame at this stage, the terminal FD is at L level, and this L level signal is inverted to H level by inverter IN4 and input to NAND circuit NA1. Also, the output of the AND circuit AN2 is also at H level at this stage.
This is also input to the NAND circuit NA1.

On the other hand, the outputs of each D-flip-flop FF1 to FF5 of the pre-purge shift register PSR are at H level, so the AND circuit AN
The output of No. 1 is also at H level. That is, in the initial state, three of the four inputs of the NAND circuit NA1 are initially set to H level, and at the same time that a heat request occurs and the output of AND circuit AN17 goes to H level, all inputs go to H level. .

As a result, the output of the NAND circuit NA1 goes to L level, the output of AND circuit AN3 goes to L level, and the output of NAND circuit NA2 goes to H level.
When this H level output is applied from terminal AO to the base of transistor Q5, the potential on the collector side is high due to the charge stored in capacitor C2 via relay K5 and resistor R2, so the transistor Q5 is immediately turned on and the charge on capacitor C2 is transferred to transistor Q
5, the terminal AI changes from H level to L level.

However, the reason why the output of the AND circuit AN17 becomes H level, that is, the output of the NAND circuit NA2 becomes H level, is due to the synchronization pulse Φ synchronized with the power supply frequency.
On the other hand, since the drive voltage applied to relay K5 is a half-wave rectified waveform of the AC power supply, it is at zero potential when transistor Q5 turns on, and relay K5 is in operation. do not.

When the level of terminal AI changes from H to L, this L
The level signal passes through buffer 5 and is connected to the inverter.
After being inverted to H level at IN1, it is applied to the data input of D-flip-flop FF11.

This D-flip-flop FF11 operates to read the level of data input at the falling edge of the synchronizing pulse Φ1, and its output becomes L level.
Therefore, the outputs of AND circuits AN4 and AN5 are both at L level, and memory M1 is not set.

Therefore, the L level signal of the memory M1 is inverted to the H level by the inverter IN4, and then input to the data input terminal of the first stage D-flip-flop FF1 of the pre-purge shift register PSR. This H level input is the clock pulse T ₀
It is sequentially shifted to D-flip-flops FF1 to FF5 in synchronization with , but during this shifting process, one of the inputs of AND circuit AN1 is at L level, so its output level becomes L level at the same time as the shift starts. , the output of the NAND circuit NA1 changes to the H level, the output of the AND circuit AN3 changes to the H level, and the output of the NAND circuit NA2 changes sequentially to the L level, and the transistor Q5 is turned off before the power supply voltage rises to the positive side. become. Therefore relay K5
never works.

Furthermore, when the power supply voltage rises after transistor Q5 is turned off, capacitor C2 is charged and terminal AI becomes H level, and the output of inverter IN1 becomes L level. Level is D-Flip Flop FF
11, its output changes to H level, and the output of AND circuit AN4 becomes H level. Therefore, buffer 5 and AND circuit AN4
The H level 2 simultaneous condition is established in the AND circuit AN5 which inputs the output of the AND circuit AN5, and when the output becomes H level, the memory M1 is set.

Note that when the output of buffer 5 becomes L level, this level is inverted to H level by inverter IN2, and then transferred to memory M2 and then to the OR circuit.
Timer TA, TB and memory M3 via OR7
are respectively supplied as reset signals.

While this operation is being performed, the prepurge shift register PSR sequentially shifts the first H input for a predetermined period of time (in this example, 30
seconds) later, the Q output of the final stage D-flip-flop FF5 becomes H level, and the output becomes L level.
This H level Q output is input to the first stage D-flip-flop FF6 of the trial shift register TSR through the AND circuit AN12 of the matching circuit MP, and is read by the clock signal _T1. Set the output to H level. As a result, both inputs of the AND circuit AN19 go to H level, and the memory M2 is set with the output thereof.

On the other hand, in the matching circuit MP, the AND circuit AN
When the output of 12 becomes H level, this output is supplied to one input of AND circuit AN13, and when the other input, clock signal _T1 , rises to H level, the output of AND circuit AN13 becomes H level. This high level output is applied to the clock input of the D-flip-flop FF5 via the OR circuit OR7. As a result, the operation timing between the pre-purge shift register PSR and the trial shift register TSR is established.

In addition, when the Q output of D-flip-flop FF5 reaches H level, some abnormality causes the terminal FD to
is at H level (false flame detection state), the output of the pre-purge shift register PSR is not transmitted to the trial shift register TSR.

(Ignition operation) Following the end of the pre-purge period, the ignition trial period begins, and when the memory M2 is set in the above operation and its Q output becomes H level, this output is added to one of the inputs of the AND circuit AN22. , is input to the base of the transistor Q2 via the terminal V1 under the conditions that the output of the AND circuit AN17 is at H level and the synchronization pulse 1 is at H level. This activates relay K2, turning on its contact K2-1, and pilot valve PV.
At the same time as the igniter IG opens, the igniter IG also operates and attempts to ignite the pilot burner.

Note that the Q output of memory M2 is the OR circuit OR6.
and to one input of the NAND circuit NA2 via the OR circuit OR2, and the output is applied to one input of the AND circuit AN4.

In the trial shift register TSR,
Based on the clock signal _T1 , the H level signal is shifted in the same way as the pre-purge shift register PSR, and the final stage D-flip-flop
When FF10 reads H level and its Q output becomes H level, this output is supplied to memory M3 via OR circuit OR9 and AND circuit AN21 to set it.

First stage D of trial shift register TSR
- The time until the H level read by the flip-flop FF6 is shifted to the final stage D-flip-flop FF10 corresponds to the pilot trial period. The pilot burner is successfully ignited within this period, and the terminal is detected by the output of the flame detector.
When FD becomes H level, the flame-on pulse generated by converter 2 is supplied to memory M3 via AND circuit AN20, OR circuit OR9, and AND circuit AN21. That is, the memory M3 is set when a flame is detected if non-recycle is selected by the sequence selector, and at the end of the pilot trial period if recycle is selected.

When the memory M3 is set, the timer TA is activated in response to its output, and after a preset post-ignition period has elapsed, the transistor Q3 is turned on and the relay K3 is turned on. As a result, the contact K3-1 is switched from the igniter IG side to the main valve V2 side.

The output of the timer TA is also supplied to the timer TB, which starts at this point, and is applied to the base of the transistor Q4 via the AND circuit AN23 after the preset delay period of the main valve V2 ends. This activates relay K4 and turns on its contact K4-1.
The main burner MV opens and enters a normal combustion state.

Also, the collector of the transistor Q2 is a terminal.
NAND circuit NA via VK and OR circuit OR2
It is connected to one input end of 2. Therefore, the H level output of memory M2 is output from AND circuit AN2.
2 to the base of transistor Q2, if transistor Q2 normally changes from off state to on state, terminal VK changes from H level to L level, but transistor Q2 has a conduction failure. In this case, the terminal VK remains at L level, and even if the output of AND circuit AN3 becomes H level, the output of NAND circuit NA2 remains at H level, transistor Q5 remains conductive, and the power supply voltage changes to the positive side. Immediately after the change to , relay K5 operates, and a shut-off operation is performed.

Further, one of the inputs of the AND circuits AN22, AN23 is supplied with 1 which is an inversion of the synchronizing pulse Φ1, so that the AND circuits AN22, AN2
3 is open, pulse signal 1 is supplied to the bases of transistors Q2 and Q4. Therefore, in reality, this pulse output drives relays K2 and K4 built into drive circuits 6 and 7 consisting of charge pump circuits.

(Normal extinguishing operation) When there is no heat demand and Akastat TH is turned off, the output of converter 1 goes to L level, so one of the inputs of AND circuit AN22 goes to L level, and transistor Q2 turns off. By turning off, relay K2 becomes inoperable, and contact K2-
1 is turned off, the pilot valve PV and main valve MV are closed, and the flame is immediately extinguished.

In addition, the TS off pulse output from converter 1 at the same time as Akastat TH turns off passes through OR circuit OR7 to memory M3 and timer TA.
Supplied to TB's reset input.

On the other hand, the memory M1 is reset by the TS on pulse, and the memory M2 is reset at the start by the reset signal supplied from the inverter IN2 when the transistor Q5 is turned on for a short time at the start. It's getting old. Also, this reset signal is an OR circuit.
Through OR7, memory M3 and timer TA,
Also supplied to TB and used to reset them.

(Operation in the event of an abnormality) If ignition fails during the pilot trial period when Akastat TH is turned on and the above sequence progresses, memory M3 is set at the end of the pilot trial period. Since the level of terminal FD, which is the output of the flame detector, remains at L, the simultaneous condition of the input of NAND circuit NA1 at H level remains satisfied, and transistor Q5 remains conductive, so relay K
A shut-off operation is performed in which No. 5 operates.

If the flame goes out abnormally during normal combustion, the terminal FD
A flame-off pulse is generated from the converter 2 by the change in the level from H to L. If the terminal SE is in the H level (recycle) state, this flame-off pulse is converted into a negative pulse by the NAND circuit NA3, and is input to the NAND NA1 via the AND circuit AN17. i.e. NAND circuit NA
1, only the level of the input receiving the output of the AND circuit AN17 changes from H to L and then back to H again. . This state is
This is equivalent to the terminal TS changing from L level to H level at the start.

In addition, the flame off pulse is an OR circuit OR1
Since it is also supplied to the reset input of memory M1 via 0, when this flame-off pulse occurs, the same operation as the initial start will be repeated.

In addition, terminal SE is L level (non-recycle)
In this state, when the terminal FD goes to L level, the simultaneous condition for the H level of NAND circuit NA1 is satisfied, and its output goes to L level. As a result, the terminal
When AO becomes H level, transistor Q5 is turned on, relay K5 is activated, and the shut-off operation is performed in the same manner as described above.

In the above embodiment, the synchronization signal Φ1 and the frequency of the driving power source of the relay K5 are set to the AC power frequency, but as long as they are synchronized with opposite phases to each other, any signal from another signal source can be used. frequency can be used.

As described above, this invention has the function of measuring the pre-purge period and pilot trial period after a heat request occurs, and performing the ignition operation according to a predetermined sequence. A fail-safe function of shifting to the safe side can be obtained with a digital circuit.
Therefore, the main parts can be integrated into ICs, and reliability can be easily improved and costs reduced.
In addition, the transistor in the shutoff means that conducts when an abnormality is detected to drive the relay conducts during the negative half cycle of the AC power supply when checking its operation, so the relay does not malfunction. It has effects such as being able to perform check operations.

[Brief explanation of drawings]

Fig. 1 is a diagram corresponding to the claims of this invention, Fig. 2 is a block diagram of a digital combustion control device according to an embodiment of this invention, and Fig. 3 shows the connection of each element controlled by the device of Fig. 2. The circuit diagram shown in FIGS. 4A and 4B is a time chart showing its operation. 1, 2... converter, 3... oscillator, 4... frequency divider, 6, 7... drive circuit, PSR... shift register for prepurge, TSR... shift register for trial, MP... matching circuit, SSH... Safety switch heater, K2, K3, K4, K5... Relay, TA, TB... Timer, M1, M2, M3...
...Memory, CSE...Clock selection circuit, TH...
Akastat, M...fan motor, PV...pilot valve, IG...igniter, MV...main valve.

Claims (1)

[Scope of utility model registration request] A first memory that is set by detecting that the shut-off means is normal when a start signal is given, and a first memory that is started upon receiving the output when this first memory is set and performs a predetermined pre-purge period. A prepurge shift register that measures the prepurge end signal and outputs a prepurge end signal at the end of the prepurge period, a second memory that is set in response to the prepurge end signal, and an output when the second memory is set. A drive circuit that operates to open the pilot valve and ignite the pilot burner upon receiving the signal, and a drive circuit that operates upon receiving the pre-purge end signal to measure a predetermined ignition trial period. a trial shift register that outputs an ignition trial end signal at the end of a period; a third memory that is set in response to a flame detection signal indicating ignition of the pilot burner or the trial end signal; A drive circuit that operates to open the main valve and ignite the main burner in response to an output signal in a state where the memory is set, and a drive circuit that operates the shut-off means when the above sequence is not performed normally. A digital combustion control device having a gate circuit that outputs an alarm signal,
The above-mentioned shut-off means includes a transistor that receives the check signal and the alarm signal obtained by reading the start signal at the falling edge of the synchronization pulse, a relay connected to the collector side of this transistor, and a relay connected to the collector side of this transistor. A drive power supply that applies a pulsed drive voltage synchronized with the synchronization pulse to the collector of the transistor via a relay, and a drive power source that outputs an H level output from the collector side when the transistor is off and a positive voltage to the collector. A digital combustion control device comprising a smoothing circuit for applying voltage.