JPS6330037Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is a combustion control device that has pre-purge timing and ignition trial timing, and when a false flame is detected after ignition failure within the trial timing, the main fuel supply device is activated. The present invention relates to a reset circuit that is applied to prevent such malfunctions.

In a combustion control device that performs ignition operation according to a predetermined control sequence, if a false flame is detected after ignition fails within the ignition trial timing, when this timing is completed, the main fuel supply device It is necessary to prevent it from operating. If this blocking action is not performed, a dangerous situation will occur in which a large amount of unignited fuel will be released.

This device has a reset circuit that performs a reset operation to stop the control sequence of the combustion control device when the ignition trial timing is completed when a false flame is detected after ignition fails within the ignition trial timing. is intended to provide.

In order to achieve the above purpose, this invention
As shown in the figure, a state determination logic circuit 10 which inputs the detection signal of the flame detection means via an inverter and also inputs the output signal from the heat requesting means;
a fan motor drive circuit that receives the output signal of the state determination logic circuit 10 and drives the fan motor;
a prepurge timer 40 that starts operating upon receiving an output signal from the state discrimination logic circuit; a memory circuit 56 that is reset by the output signal of the state discrimination logic circuit 10 and set by a time-up signal of the prepurge timer 40; an ignition trial timer 50 that starts operating in response to the time-up signal and opens the pilot valve to operate the igniter; an AND gate 14 that receives the time-up signal of the pre-purge timer 40 and the time-up signal of the ignition trial timer 50; A first NAND gate 61 which logics the set signal of the memory circuit 56, the output signal of the AND gate, and the detection signal of the flame detection means and operates the main valve drive circuit when the logic is established, the state determination logic circuit 1
0 is input to a second NAND gate 15 which inputs the output signal of the inverter, the output signal from the heat requesting means, and the output signal of the AND gate, and the output signal of the inverter and the output signal of the memory circuit. It is composed of an OR gate 18 and a third NAND gate 17 which receives the output signal of the second NAND gate and the output signal of the OR gate.

In the above configuration, when there is no flame and no heat request, the prepurge timer 40 and the ignition trial timer 50 are not driven, so the AND
The output of the gate 14 is "1", and therefore the output of the NAND gate 15 is also "1". Furthermore, since the signal is "1", the output of the OR gate 18 is also "1", and therefore the output of the NAND gate 17 is "0".

When there is a heat request in this state, the output of the heat request means is "1", the output of the AND gate 14 is "1", the output of the NAND gate 15 is "0",
Since the output of OR gate 18 becomes "1",
The output of the NAND gate 17 becomes 1.

“0” → “1” of the output of this NAND gate 17
The pre-purge timer 40 is operated at the same time as the fan motor is driven by the change in the pre-purge timer 40. While the pre-purge timer 40 is counting, the output of the AND gate 14 is “0”.
Therefore, the output of the NAND gate 15 returns to "1". Further, since the output of the OR gate 18 is 1 when =1, the output of the NAND gate 15 returns to 1, and the output of the NAND gate 17 also returns to "0".

When the prepurge timer 40 times up,
At the same time as 1 is set in the memory circuit 56, the ignition trial timer 50 is started, and while the ignition trial timer 50 is being driven, the igniter and pilot valve operate to start the ignition operation.

When ignition is achieved, the flame signal F=1 (=0), and the ignition trial timer times up, all inputs to the AND gate 14 become 1, so the output of the AND gate becomes 1. At this time, F
is 1 and the output of the memory circuit 56 is "1", so the output of the NAND gate 61 becomes "0" and the main valve opens.

Since the ignition is on, the signal is “0”.
Therefore, since the output of the NAND gate 15 is also "1" and the output of the memory circuit 56 is 1, the output of the OR gate 18 is also "1". Therefore, the output of the NAND gate 17 becomes 0 and the memory circuit 56 is not reset. Therefore, the output of the NAND gate 61 remains at 0, the main valve opens, and normal combustion begins.

If ignition does not occur during the ignition trial, the memory circuit 56 is set to "1" when the pre-purge timer 40 times up, and when the ignition trial timer 50 times up, the output of the AND gate 14 becomes 1, but the signal F Since it is 0, the output of the NAND gate 61 is 1. Therefore, the main valve will not open.

At this time, the signal is 1, the heat request signal is 1,
Since the output of AND gate 14 is 1, NAND
The output of gate 15 is 0. Also, signal=1
Therefore, the output of the OR gate 18 is also 1.
The output of OR gate 18 is "1" and the output of NAND gate 1
Since the output of NAND gate 17 becomes "1" from the output of NAND gate 4, this output causes memory circuit 56 to
Reset to .

Therefore, if ignition does not occur during the ignition trial, the memory circuit 56 is reset to 0, so even if a false flame is generated and the signal F=1 (=0) thereafter, the output of the memory circuit 56 remains. For,
The output of the NAND gate 61 becomes 1 and the main valve does not open. Therefore, it is fail-safe against false flames.

Embodiments of the digital combustion control device of the present invention will be specifically described below with reference to the drawings.

FIG. 2 shows a combustion integration control device that performs basic control sequence operations commonly used in various combustion control devices. Note that, in addition to the safety switch section and load relay drive section, devices to be connected to this integrated control device, such as a flame detection circuit or a thermostat starting switch, are not shown in the figure. Various connections can be considered for the blower, valve, pump, igniter, etc. controlled by the load relay, one example of which is shown in FIG. 3, and its operation will be described later.

In the figure, reference numeral 10 denotes a state determination circuit, which detects an output signal from a thermostat or manual start switch (not shown), that is, a heat request signal 11, and an inverted flame signal 13, which is an inversion of the output signal from a flame detection circuit (not shown). , AND gate 1 described later
Input three signals with output 16 of 4
A NAND gate 15 is provided. here,
The heat request signal 11 is “1” when there is a heat request.
On the other hand, the flame detection circuit outputs "1" when there is flame and "0" when there is no flame, so the inverted flame signal 13 outputs "0" when there is flame. If not, set “1” to NAND15
is given to the input. On the other hand, this inverted flame signal 1
3 and a memory circuit M3 indicating a prepurge end signal;
The output of the OR gate 18 inputting the signal 20 of 56 and the output of the NAND gate 15 mentioned above are as follows.
It is added to another NAND gate 17, which outputs the output of the state discrimination logic circuit. Further, 28 is a clock generator, which is a clock generator for the commercial AC power supply 2.
9 generates the pulse of clock 1, and this pulse passes through a frequency divider 27 to generate two clock signals of clock 2. The clock 2 synchronizes the timing at which the heat request signal from the start switch is supplied to the control device, so that the safety switch circuit 21 operates at regular timing.

The safety switch circuit 21 includes a transistor _Q1 ,
It consists of a safety switch load 24 connected between its collector and the power supply. The safety switch load 24 is
It is a heating drive load for a predetermined interval type cut-off switch, such as an instantaneous type cut-off switch or a thermally-responsive switch. On the other hand, in order to sense the switch state of the transistor 23, its collector 25
and a state sensing signal C ₁ 26 from a first timer circuit 40, which will be described later, are provided, and the output thereof is input to an S/R flip-flop 31 which acts as a latch circuit.
This S/R flip-flop 31 is given the clock 1 signal synchronized with the power supply commercial frequency mentioned above, and its output is passed through a NOT gate 32 and
The outputs of gate 33 and also NOT gate 32 are applied to another latch circuit M5,17. AND
The output of the AND gate 27 is directly applied to the gate 33, and the output of the AND gate 33 is further applied to the memory circuits M1 and 34.

On the other hand, the output of the AND gate 27, the memory output 34', and another memory circuit M to be described later.
AND with memory output 39 of 3,56 as input
A gate 37 is provided, and its first valve driving output is
Load relay drive circuit 7 provided outside the integrated control unit
Turn on/off transistor 71 of 0 and relay 7
Open and close 5. Further, another AND gate 35 is provided which receives as inputs the output of the memory circuit M1, 34 and the inverted output 3 of the output 39 of the memory circuit M3, 56, and also on the output side of this AND gate 35, another memory circuit M2, 36 is connected. A combustion fan motor drive is output from the output, which turns on/off the transistor 72 of the load relay drive circuit 70 and energizes the relay 76.

On the other hand, the output of the NOT circuit 32 is the latch circuit M5,
17, and an AND gate 18 whose inputs are the output of the latch circuit M5, 17 and the clock 2.
The output of is applied to the modified S/R flip-flop of the first timer circuit 40.

On the other hand, the first
The timer circuit 40 receives both the input of the memory output 2 indicating the fan motor drive state via the NOT gate 42 and the time setting terminal TP input, and the output of the NAND 41 is connected to multiple S/R flip-flops. A "0" signal is supplied to a timer circuit in which 42 clocks are connected in cascade, and a "0" shift register is configured by the clock 2 signal. Outputs F ₁₁ and F ₁₂ are output from the flip-flop outputs of each stage. ，
F ₁₃ , . . . F _o 46 are connected to the inputs of the AND gate 14 to form a first timer circuit. On the other hand, a pseudo flame latch circuit FL43 composed of a NOT gate 44 and a NAND gate 45 is connected to the output of the stage change of the flip-flop 42, and the NAND gate 45 of each pseudo flame latch circuit FL43 is connected to the
An inverted flame signal is applied. The output of the final stage flip-flop 42 is sent to the AND gate 14.
In addition to being supplied with F ₁ n, it is also used as the input signal C1, 26 of the AND gate 27 mentioned above, and also as an input signal of the second timer circuit 50 that secures the next stage ignition trial timing. Further, the second timer circuit 50 performs almost the same timer operation as the first timer circuit 40, but the first stage flip-flop
Pseudo flame latch circuit 5 is connected only to the output of flop 51.
2 is given, and it is not provided after the next stage. Second
The flip-flop circuit of the timer circuit 50 may be a normal S/R flip-flop circuit, but since a fail-safe flip-flop circuit is used here, clock 2 is applied to the flip-flop circuit through the NOT gate 53.・Flop 5
1 and the flip-flop 51' added without going through the NOT gate 53 are connected alternately.
Similar to the first timer circuit 40, the output of each stage is
It is added to the input of AND gate 14.

On the other hand, the input signal of the final stage flip-flop 42 of the first timer circuit, the output signal of the NOT gate 44 of the final stage pseudo flame latch circuit 43, and the first stage flip-flop 51 of the second timer circuit
An AND gate 55 is provided which inputs the output signals of the memory circuits M3 and M3, respectively.
The state is stored in step 56. This memory circuit 56 determines whether or not the pre-purge timing has ended.

Furthermore, the flip-flop outputs of the first and second timer circuits are connected to the inputs of the AND gate 14, and the outputs are added to the AND gate 16 only when all of these inputs become "1".

The output of the AND gate 14 is the NAND
15, and is also connected to a third timer circuit 60 for providing pilot-only timing, ie, pilot stabilization time, at the next stage. That is, the flame signal F13' (not inverted) indicating that a flame has been established, and the AND gate 14
A plurality of cascade-connected S/R flip-flops 6 are connected to a NAND gate 61 which receives the output 16 of the floppy circuit and the prepurge end signal 39 as inputs.
2 is driven by clock 2, NOT gate 63
gives an output V2 that drives the second valve etc., and turns on/off the transistor 73 of the load relay drive circuit 70.
Turn off and energize relay 77.

Reference numeral 80 is a recycle/non-recycle setting circuit, which is used to set "recycle/non-recycle" through the external set terminal 85 when it is desired to cause the control device to perform a recycle operation, that is, when it is desired to automatically perform the ignition sequence again even after the flame has been extinguished. When you want to perform non-recycle operation, give "0". In addition, the outputs M1 and M2 of the two memory circuits M1 and 34 and the memory circuits M2 and 36 are input to an OR gate 83, and the outputs are read out to the S/R flip-flop 82 using the inverted flame signal 13, and the flip-flop An AND circuit whose inputs are the output of the flop 82, the external set signal 82, and the prepurge timing signal M3.
The output of the gate 84 resets the memory circuits M1, M2, and M3 when performing a recycling operation, returning the control device to a restartable state.

Next, the operation of such a configuration will be explained together with the operation of the load drive circuit shown in FIG. 3 as an example.

Figure 3 shows the fan motor 2, pilot valve 3,
This is a load drive circuit for a gas burner in which a main valve 5 and an igniter 4 are shown with well-known connections. In addition, the first
By using the load relay drive circuit shown in the figure, various known load drive circuits for alternators can also be controlled by this control device, but here, an example of the most general connection for a gas combustor will be explained.

First, assume that all gate circuits are powered and energized, that there is no flame in the burner, and that there is no heat demand on the start switch or thermostat. At this time, AND gate 1 is output from the first and second timer circuits 40 and 50.
Since a signal of "1" is applied to all input terminals of the AND gate 14, the output of the AND gate 14 is "1".

Therefore, the NAND gate 15 of the state discriminating circuit 10 is set to ="1" indicating that there is no flame.
and the output "1" of the AND gate 14 are applied. In this state, the output of the NAND gate 15 is 1 because there is no heat demand, and the output of the OR gate 18 is 1 because there is no flame, so the output of the NAND gate 17 is "0", and the output of the safety switch circuit 21 is "0". Since the transistor Q1 is not energized and the first timer circuit 40 is also not energized, the signal C1="1" from the final stage S/R flip-flop 42 and the safety switch circuit 21 are energized. Signal “1” indicating that the
is added to the AND gate 27, and its output is “1”
is given to the S/R flip-flop 31.
The output of the NOT gate 32 remains “0” and the AND
Since the gate 18 does not open, the operation of the first and second timer circuits is stopped. Therefore, the outputs of the memory circuits M1, 34 and M2, 36 are both "0".

When the thermostat outputs a heat request signal "1" in such a state, the latch circuits M4 and 12
In synchronization with clock 2, which is constantly added to
A heat request signal “1” is applied to the NAND gate 15. Then, the output of NAND gate 15 is “1”
to “0”, the output of NAND gate 17 is “0”
to “1”, and the output of the AND gate 27 is
Since its input terminal 25 becomes "0", its output becomes "0". For this reason, flip-flop 31
calls in this “0” and connects it to the IN of inverter 32.
2 output is set to "1", but since "0" is given to the other input of AND gate 33, there is no change after that AND gate 33. However, since the output "1" of the inverter 32 is given to the latch circuit M5, 17, the output "1" is applied together with the clock 2.
From the output of the AND gate 18, the clock 2 is directly applied to each flip-flop 42, 51 of the first and second timer circuits. Therefore, when the first clock 2 is applied, the first stage S/R flip-flop 42 of the first timer circuit is switched to the NAND
The “0” output of the gate 41 is called in. Since the inverted flame signal "1" is added to the pseudo flame latch circuit 43, the pseudo flame latch circuit 43 outputs the output of the S/R flip-flop 42 as it is, and the output F11 of the first stage is " ₁ ". 0'' output is applied to AND gate 14.

The above operations are performed simultaneously when the heat request signal 1 and the clock 2 operate the NAND gate 15 in synchronization. Clock 2 is a pulse generated from an AC power supply by a clock generator 28 at a frequency of approximately 100 Hz, which is twice the frequency of the AC power supply.
This frequency is divided to generate a pulse of about 1 second. When there is a heat demand, F ₁₁ is set by a pulse on clock 2.
becomes 0, so the output 16 of the AND gate 14 is inverted from "1" to "0", and this "0" signal becomes the start instruction signal for the prepurge operation. This “0”
Since the signal is applied to the NAND gate 15,
The output of NAND gate 15 becomes “1” again,
The output of NAND gate 17 becomes “0”, and
The output of AND gate 27 is set to "1" again. Therefore, two "1" signals enter the AND gate 33, so the memory circuit 34 is latched to "1" for the first time at this point, and the "1" signal is applied to the AND gate 35. Since the AND gate 35 is further supplied with the inverted output 3="1" of the memory circuit 56, which indicates that the pre-purge timing has not yet been completed, the memory circuit 36 is also latched at "1". Therefore, a signal to drive the fan motor 2 (Fig. 3) from the integrated control device is output from the M2 output terminal, turns on the transistor Q3, and turns on the relay 1.
R is driven to start the operation of the fan motor 2.

In this way, as soon as the heat request signal "1" is applied to the state determination circuit 10, the memory circuits M1 and M2
The reason why the safety switch drive circuit 21 is operated for a time determined by the clock 2 without driving the safety switch drive circuit 21 is to check whether the safety switch drive circuit 21, that is, especially the transistor Q123, is functioning normally. That is, AND gate 27
When the output of the memory circuit M2, 36 does not perform a one-cycle operation of "1" → "0" → "1",
is not latched, the prepurge operation does not start, and the fan motor 2 is not driven. Particularly in this embodiment, when a conduction failure occurs in the externally connected transistor 23, the safety switch is shut off. In addition,
During this one-cycle operation, the transistor 23 is driven for a time determined by the pulse timing of the clock 2, but it is possible to select the one in which the safety cut-off switch 24 is not pulled in at this timing, and this invention is also applicable to this invention. are selected. Although this embodiment shows the operation check of only the safety switch circuit, it is also possible to check the operation of the load relay drive circuit.

Now, the output of the discrimination circuit 10 mentioned above is "1"
→ After the cycle operation of "0" → "1", the contact 1R1 of the relay 1R shown in FIG. operate sequentially. Since each flip-flop 42 of the first timer circuit 40 is given clock pulses 2 at intervals of about 1 second, the "0" signal of the output _F11 is sent to the next stage _F12 as a "0".
is sent, and then shifted to the next flip-flop in sequence with the next clock pulse 2. Therefore, one of all inputs of AND gate 14 is “0”
Since the signal is applied, the output 16 of that AND gate 14 is connected to the first and second timers 40 and 5.
0 flip-flop 42 or 5
1 outputs "0" indicating that timekeeping is in progress. When the pre-purge period ends, the first timer circuit 40
Output of the final stage S/R flip-flop circuit
When the "0" signal is shifted to _F1n47 , all three input signals of the AND gate 55 become 1, so that the memory circuits M3 and 56 are latched to "1". but,
The pulse of clock 2 is always flip-flop 5.
Since it is also given to 1,51′, the final output F ₁ n
is then supplied to the second timer circuit for ignition trial timing, and the flip-flops 51,5
The "0" shift operation continues sequentially to the outputs F ₂₁ , F ₂₂ . . . F ₂ m of 1'.

On the other hand, at the same time that the memory circuit 56 is latched to "1", this output M3 (=1) is applied to the input terminal 39 of the AND gate 37. Since the other inputs 48 and 49 of the AND gate 37 are applied with a signal "1" indicating that the motor output is energized and that the safety switch is normal, the output of the AND gate 37 is “1”
and energizes transistor 71 and relay 2R.

As shown in FIG. 3, since the contact 2R1 of the relay 2R is closed, the pilot valve 3 is energized, and the ignition device 4 is preliminarily connected to the flame detection circuit output relay contact FC-6 outside the integrated control device. operate at the same time.

Here, if a flame is established in the combustor, a flame detector (not shown) detects the flame, inverts the relay contact FC, and sends a signal of inverted flame signal = 0 to the state determination circuit 10 to the NAND gate 15. Apply. However, at this point, the ignition trial time has not yet been completed, so the relay 3R is not energized, and the output of the AND gate 14 is "0" indicating that the second timer circuit 50 is in operation. Since the output is applied to the NAND gate 15, the output of the NAND gate 17 of the state discrimination circuit 10 remains "0" without any change, and the main valve 4
is not energized.

However, when the second timer circuit 50 times out, the AND gate 14
Since there is no "0" input from the flip-flops constituting the second timer circuit 50, all the inputs become "1", and a "1" signal indicating that time has elapsed is outputted. The second timer circuit 50 ends the ignition trial timing.
When the time-up occurs, the output "1" is output, but in the status determination circuit 10, since =0 indicating that the flame is established is added to the NAND 15, there is no change in the output.

On the other hand, at this point, the AND gate 14 is “1”.
Since the "1" output of the memory circuit M3, 56 and the flame signal F=1 are applied to the NAND gate 61, the "0" output is the S/ of the third timer circuit 60 which ensures the pilot only time. R flip
This “0” signal is applied to the flop 60, and is shifted with the pulse of clock 2, and after a predetermined period of time, a “1” is applied to the V2 output terminal via the NOT gate 63.
A signal is given to energize relay 3R. Therefore, in FIG. 3, flame relay contact FC and relay contact 3R1, which have already been reversed due to the establishment of flame,
The main valve 4 opens via the pilot flame, and the main fuel is ignited by the pilot flame, resulting in steady combustion. The purpose of providing the pilot-only time is to ensure that only the fuel supply to the pilot valve establishes ignition and creates a stable state, then the main valve opens and normal combustion begins. This normal combustion operation sequence is shown in FIG. 4a. In addition, in FIG. 2, the AND gate 14
without applying the output of NAND to the NAND gate 61.
The input of the gate 61 is connected to the memory output 39 and the flame output 1.
3', the pilot will start from the moment the flame is established, regardless of the ignition trial time.
You can secure the only one.

Next, the ignition failure behavior in the ignition trial will be described. Until the ignition trial timing,
Assuming it is normal as above, AND gate 3
7 is energized, but after the ignition trial timing elapses, the second timer circuit 50 times up and the output of the AND gate 14 is inverted from "0" to "1", so the inputs of the NAND gate 15 are all "1". , the output of NAND gate 17 is “1”
, the safety cutoff drive circuit 21 operates, and the third
The SSW shown in the figure opens and all power is cut off when used for non-recycling. Note that when used as a recycling operation, the safety switch driving section 24 may not be provided, and the cycle discrimination circuit 80 may be operated to repeat the initial sequence again. Figure 4b shows the case where the safety switch is activated.

Next, we will discuss the case where there is a pseudo flame. =
0, so the thermostat output is “1”
Since the state determination logic circuit 10 and the load latch control circuit 30 do not operate in one cycle, the control sequence does not proceed. Furthermore, if a pseudo flame is generated during pre-purge, the flame signal to the pseudo flame latch circuit 43 provided between each stage of the first timer circuit 40 becomes 0, so the shift operation is continued between any stage. The latch circuit 43 eliminates the "0" signal present. Therefore, a "1" signal indicating the stop of the timer operation is outputted from the AND gate 14, and the safety switch cutoff circuit is driven through the discrimination logic circuit 10 to stop the sequence operation. This situation is shown in FIG. 4c.

"In Figures 4a, 4b, and 4c, a is the power switch, b is the high limit switch, c is the thermostat, d is the motor, e is the ignition transformer, f is the pump, g is the flame, and h is the In addition, PIT is the pre-ignition timing, ITT is the ignition trial timing, and SST is the safety switch timing.'' As described above, according to this invention, when the ignition trial timing is completed, the If a false flame exists, the memory circuit M3 is reset by the output of the state discriminating logic circuit that detects this. Since it is assumed that the memory circuit M3 is set in order to operate the main fuel supply system, once a false flame is detected, the control sequence will not proceed; A situation in which a large amount of unignited fuel is released is reliably prevented.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the main parts of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention, and Figure 3 is a circuit diagram of a load drive circuit for a gas combustor controlled by the output of the device. , FIGS. 4a to 4c are sequence diagrams showing the operation sequence of each part of the device. 10... Status determination logic circuit, 20... Safety switch drive circuit, 30... Load control latch circuit, 4
0...First timer circuit, 50...Second timer circuit, 60...Third timer circuit, 70...Load relay drive circuit, 80...Recycle/non-recycle setting circuit.

Claims (1)

[Scope of utility model registration request] A state determination logic circuit that inputs the detection signal of the flame detection means via an inverter and also inputs the output signal from the heat requesting means, and a fan motor drive circuit that receives the output signal of this state determination logic circuit and drives the fan motor. a pre-purge timer that starts operating in response to an output signal of the state-determining logic circuit; a memory circuit that is reset by the output signal of the state-determining logic circuit and set by a time-up signal of the pre-purge timer; an ignition trial timer that receives a signal and starts operating, opens a pilot valve and operates an igniter;
An AND gate inputs the time-up signal of the pre-purge timer and the time-up signal of the ignition trial timer, and the set signal of the memory circuit, the output signal of the AND gate, and the detection signal of the flame detection means are logically connected, and when the logic is established, a first NAND gate that operates the main valve drive circuit, and a second NAND gate that inputs the output signal of the inverter, the output signal from the heat requesting means, and the output signal of the AND gate; and an OR gate that receives the output signal of the inverter and the output signal of the memory circuit, and a third NAND gate that receives the output signal of the second NAND gate and the output signal of the OR gate. Reset circuit for combustion control device.