JPS6210535U - - Google Patents

Info

Publication number
JPS6210535U
JPS6210535U JP10051785U JP10051785U JPS6210535U JP S6210535 U JPS6210535 U JP S6210535U JP 10051785 U JP10051785 U JP 10051785U JP 10051785 U JP10051785 U JP 10051785U JP S6210535 U JPS6210535 U JP S6210535U
Authority
JP
Japan
Prior art keywords
speed
converters
series
parallel type
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10051785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10051785U priority Critical patent/JPS6210535U/ja
Publication of JPS6210535U publication Critical patent/JPS6210535U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の直並列型AD変換器の一実
施例のブロツク図、第2図は従来例のブロツク図
、第3図、第4図はこの考案の要部の実施例の回
路図である。 1:アナログ入力信号、2:サンプルホールド
回路、3:上位のAD変換器、4:遅延回路、5
:引算器、6:DA変換器、7:下位のAD変換
器、8:バツフアアンプ。
Fig. 1 is a block diagram of an embodiment of the serial-parallel AD converter of this invention, Fig. 2 is a block diagram of a conventional example, and Figs. 3 and 4 are circuit diagrams of an embodiment of the main part of this invention. It is. 1: Analog input signal, 2: Sample hold circuit, 3: Upper AD converter, 4: Delay circuit, 5
: Subtractor, 6: DA converter, 7: Lower AD converter, 8: Buffer amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アナログ信号のデジタル化を、複数段のAD変
換器を用いて行なう直並列型AD変換器において
、次段のAD便換を行なうために必要となる遅延
回路に、複数個縦続接続した高速、高精度のバツ
フアアンプを用いる事を特徴とする直並列型AD
変換器。
In series-parallel type AD converters that digitize analog signals using multiple stages of AD converters, multiple high-speed, high-speed, high-speed A series-parallel type AD characterized by the use of a precision buffer amplifier.
converter.
JP10051785U 1985-07-03 1985-07-03 Pending JPS6210535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10051785U JPS6210535U (en) 1985-07-03 1985-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10051785U JPS6210535U (en) 1985-07-03 1985-07-03

Publications (1)

Publication Number Publication Date
JPS6210535U true JPS6210535U (en) 1987-01-22

Family

ID=30970417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10051785U Pending JPS6210535U (en) 1985-07-03 1985-07-03

Country Status (1)

Country Link
JP (1) JPS6210535U (en)

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