JPS62104305A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To reduce a potential drop at an input terminal without increasing MOS transistors (TR) in size by connecting the gates of the 1st and the 2nd MOS TRs which have the same potential in common and connecting a constant voltage source between the gate and drain of the input-side MOS TR. CONSTITUTION:A potential difference is given as a constant voltage source 5 between the gate and drain of the MOS TR 1 by using the gate-source voltage of an N channel MOS TR 6. Namely, the source of the MOS TR 6 is connected to the power source terminal, the gate is connected to the drain of the MOS TR 1, and the drain is connected to the common connection point of the gates of the MOS TRs 1 and 2. Then, a bias current source 7 is connected to the drain of the MOS TR 6 and the ground terminal. Therefore, the gate-source voltage of the MOS TR 1 becomes higher than the drain-source voltage and the drain-source voltage is lower than when the drain potential and gate potential are equal to each other.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a current mirror circuit.

[Technical Background of the Invention 11] A conventional current mirror circuit is shown in FIG. In the figure, reference numeral 1.2 denotes a P-channel MoS transistor, each gate of which is connected in common, and each source connected to a predetermined power supply terminal. The data and drain of MOS transistor 1 are connected, and input current source 3 is connected between this connection point and the ground terminal.

The drain of MOS transistor 2 is connected to output terminal 4.

In the current mirror circuit configured in this way, the MOS
Due to the drain-gate short circuit characteristic of the transistor 1, a gate-source voltage corresponding to the input current IIN from the input current source 3 is applied to the MoS transistor 2, and an output current Iour proportional to the input current 11N is obtained from the output terminal 4. It will be done.

[Background technology and technical problems] In the conventional circuit, as the input current IIN increases,
The voltage between the drain/gate and source of the MoS transistor 1 becomes large, which interferes with the operation of the input current source 3. Another drawback is that the gate width must be increased in order to prevent the voltage between the drain/gate and source from increasing. Furthermore, increasing the gate width increases parasitic capacitance, and when the input current IIN is alternating current, there is a drawback that the operating speed becomes slow.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide a current mirror circuit that can reduce the potential drop at the input terminal without increasing the size of the MOS transistor. It is about providing.

[Summary of the Invention] In order to achieve the above object, the present invention connects a constant voltage source between the gate and drain of the MoS transistor on the input side to increase the voltage between the gate and source. This makes it possible to obtain the same effect as increasing the size of the transistor without increasing the size of the transistor.

[Embodiments of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the same parts as in FIG. 8 are denoted by the same reference numerals, and the explanation thereof will be omitted, and only the different parts will be explained in detail.

FIG. 1 shows the principle of the present invention, in which a constant voltage source 5 is connected between the gate and drain of a MOS transistor 1 so that the voltage between the gate and source is higher than the voltage between the drain and source. be. In this way, by increasing the gate-source voltage, the same effect as when increasing the size of the MOS transistor can be obtained without increasing the size of the MOS transistor.

FIG. 2 shows a first specific example of the circuit of the present invention, and shows M
Between the gate and drain of the OS transistor 1, a constant voltage source 5 is connected between the gate and drain of an N-channel MoS transistor 6.
A potential difference is given using the voltage between the sources. That is, the source of the MOS transistor 6 is connected to a predetermined power supply terminal, the gate is connected to the drain of the Mo8 transistor 1, and the drain is connected to the MOS transistor 1.
Each gate of transistor 1.2 is connected to a common connection point. A bias current source 7 is connected between the drain of the MOS transistor 6 and the ground terminal.

By connecting the MOS transistor 6 in this way, the gate-source voltage of the MOS transistor 1 becomes larger than the drain-source voltage, and the drain-source voltage of the MoS transistor 1 is such that the drain potential and the gate potential are equal. smaller than before.

FIG. 3 shows a second specific example of the circuit of the present invention.
An NPN bipolar transistor 8 is connected as a constant voltage source 5 between the gate and drain of the OS transistor 1 to provide a potential difference and reduce the voltage drop at the drain. That is, the collector of transistor 8 is connected to a predetermined power supply terminal, the base is connected to the drain of MoS transistor 1, and the emitter is connected to M
The respective gates of oS transistors 1 and 2 are connected to a common connection point. A bias current 11!7 is connected between the emitter of the transistor 8 and the ground terminal. Even in this manner, the same purpose as in FIG. 2 can be achieved.

FIG. 4 shows a third specific circuit example of the present invention. This is a circuit example in which the polarity of each transistor in FIG. The explanation will be omitted.

FIG. 5 shows a fourth specific circuit example of the present invention. This is a circuit example in which the polarity of each transistor in FIG. The explanation will be omitted.

FIG. 6 shows a graph of current-voltage characteristics when the gate and drain of MOS transistor 1 in FIG. 8 are connected and used as a two-terminal element.

As shown in this graph, in order to increase the train current 1o while keeping the drain-source voltage VD9 in the same state, the transistor size must be increased. Therefore, by connecting the constant voltage source 5 as shown in Fig. 1,
The gate-source voltage of the MOS transistor 1 is made larger than the gate-source voltage of the MOS transistor 1 shown in FIG. 8 by the magnitude of the constant voltage source 5. FIG. 7 shows a current-voltage characteristic graph of the MOS transistor 1 when a constant voltage of 8!5 is connected. As can be seen from this graph, the current-voltage characteristics of the MOS transistor 1 exhibit characteristics similar to those when the 1-transistor size is increased. Therefore, by connecting the constant voltage H5, it is possible to reduce the voltage drop and obtain the same effect as when the transistor size is increased.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a current mirror circuit that can reduce the potential drop at the input terminal without increasing the size of the MOS transistor.

[Brief explanation of drawings]

1 to 7 show an embodiment of the present invention,
FIG. 1 is a circuit diagram for explaining the principle, FIGS. 2 to 5 are circuit diagrams showing specific circuit examples, FIG. 6 is a graph showing the current-voltage characteristics of the MOS transistor in FIG. 8, and FIG. FIG. 7 is a graph showing the current-voltage characteristics of the MoS transistor shown in FIG. 1, and FIG. 8 is a circuit diagram showing a conventional current mirror circuit. 1.2...MOS transistor, 3...
・Input current source, 4... Output terminal, 5...
・Constant voltage source, 6...MOS transistor, 7.
...Bias current source, 8...Bipolar transistor. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] The gates of the first and second MOS transistors having the same polarity are connected in common, and a constant voltage source is provided between the gate and drain of the first MOS transistor so that the voltage between the gate and source is higher than the voltage between the drain and source. 1. A current mirror circuit, characterized in that the current mirror circuit is configured such that an input current is supplied to the drain of the first MOS transistor, and an output current is obtained from the drain of the second MOS transistor.