JPS62104145A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62104145A
JPS62104145A JP60245113A JP24511385A JPS62104145A JP S62104145 A JPS62104145 A JP S62104145A JP 60245113 A JP60245113 A JP 60245113A JP 24511385 A JP24511385 A JP 24511385A JP S62104145 A JPS62104145 A JP S62104145A
Authority
JP
Japan
Prior art keywords
case
corners
silicon gel
bonding
gel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60245113A
Other languages
Japanese (ja)
Other versions
JPH0418468B2 (en
Inventor
Yoshio Takagi
義夫 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60245113A priority Critical patent/JPS62104145A/en
Publication of JPS62104145A publication Critical patent/JPS62104145A/en
Publication of JPH0418468B2 publication Critical patent/JPH0418468B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent rise-up of gel and to make bonding between a case and an epoxy resin excellent, by providing roundish parts at four corners of the case or providing ribs at intermediate high positions of the four corners. CONSTITUTION:For example, bonding of a base electrode and an emitter electrode 5 is performed with aluminum wires 8 and 9. A case 2 is stuck to a base plate 1 with a bonding agent. Thereafter, silicon gel 10 is injected fro protecting a chip and aluminum. At this time the insides of the four corners of the case 2 are made to be round shape. Then, the following adverse phenomena are prevented: rise-up of the silicon gel 10 up to the upper part of the case 2 due to the surface tension of silicon gel; poor bonding between the case 2 and an epoxy resin 11 at the time of sealing, e.g., sealing with the epoxy rein; and adverse effect with respect to moisture resistance. When ribs 30 are provided at the intermediate parts of the roundish parts, the rise-up of the silicon gel is completely eliminated and the effect is further increased. When simultaneous machining is performed during the molding of the case, the price is not increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関し、とりわけ樹脂封止形半
導体装置のケースの改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to improvements in the case of resin-sealed semiconductor devices.

〔従来の技術〕[Conventional technology]

第４図は、従来の半導体モジュールの平面図であり、こ
こでは、ｌ＠子入り電力用半導体モジュールを例にして
示している。図において、１はベース板、２はケース、
３は絶縁基板、４はベース電極、５はエミッタ電極、６
はモリブデン坂、７はシリコンチップ、８はベースアル
ミニウムワイヤ、９はエミッタアルミニウムワイヤであ
る。FIG. 4 is a plan view of a conventional semiconductor module, and here, a power semiconductor module with a l@-electron is shown as an example. In the figure, 1 is the base plate, 2 is the case,
3 is an insulating substrate, 4 is a base electrode, 5 is an emitter electrode, 6
is a molybdenum slope, 7 is a silicon chip, 8 is a base aluminum wire, and 9 is an emitter aluminum wire.

第５図は、第４図の断面図であり、ベース、エミッタア
ルミニウムワイヤ８，９をアルミニウムワイヤボンディ
ングし、ケース２を接着剤でベース板１に接着した後、
シリコーンゲル１０の注入を行い、キュアー後にエポキ
シ樹脂１）を注入し、キュアーを行う。FIG. 5 is a sectional view of FIG. 4, and after aluminum wire bonding the base and emitter aluminum wires 8 and 9 and bonding the case 2 to the base plate 1 with adhesive,
Silicone gel 10 is injected, and after curing, epoxy resin 1) is injected and cured.

（発明が解決しようとする問題点〕 従来の半導体装置は、以上のように構成されており、ケ
ース２接着後、シリコンゲル１０を注入すると、表面張
力によってケース４隅からシリコンゲルがはい上がり、
このため次にエポキシ樹脂を注入した時に、ケースの４
隅においてケースとエポキシ樹脂の接着が悪くなるとい
う問題点があった。(Problems to be Solved by the Invention) The conventional semiconductor device is configured as described above, and when the silicon gel 10 is injected after the case 2 is bonded, the silicon gel crawls up from the four corners of the case due to surface tension.
For this reason, the next time you inject epoxy resin,
There was a problem in that the adhesion between the case and the epoxy resin deteriorated at the corners.

この発明は、上記のような問題点を解消するためになさ
れたもので、ゲルのはい上がりを防止できる半導体装置
を提供することを目的とする。This invention was made to solve the above-mentioned problems, and an object of the invention is to provide a semiconductor device that can prevent gel from creeping up.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、ケースの４隅にＲ（アー
ル）部を設けるか、またはケースの４隅の中間高さ位置
にリブを設けるようにしたものである。In the semiconductor device according to the present invention, R portions are provided at the four corners of the case, or ribs are provided at intermediate height positions at the four corners of the case.

〔作用〕[Effect]

この発明においては、ケースの４隅にＲ（アール）部を
設けるか、またはケースの４隅の中間高さ位置にリブを
設けたから、ゲルのはい上がりはほとんど発生しない。In this invention, since R portions are provided at the four corners of the case or ribs are provided at intermediate height positions at the four corners of the case, gel creep hardly occurs.

〔実施例〕 以下、この発明の一実施例を第１図ないし第３図を用い
て説明する。[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

第１図は、本発明の一実施例による半導体装置を示す平
面図、第２図、第３図は、ケース部分の詳細を示す断面
図である。図中、第４図、第５図と同一符号は同一部分
を示す。第２図において、２０はケースの４隅に上から
下まで同じ形状に形成したＲ（アール）部である。第３
図において、３０はＲ（アール）部２０の中間に設けた
リブである。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing details of a case portion. In the figure, the same reference numerals as in FIGS. 4 and 5 indicate the same parts. In FIG. 2, reference numeral 20 indicates R portions formed in the same shape from top to bottom at the four corners of the case. Third
In the figure, 30 is a rib provided in the middle of the R (R) portion 20.

次に作用効果について説明する。Next, the effects will be explained.

第１図において、ベース板１上に絶縁基板３とエミッタ
電極４、ベース電極５を載せ、それらとは別にベース板
１の上に、あらかじめモリブデン板６の上に高温ハンダ
付けされたシリコンチップ７を載せ、同時に低温ハンダ
によりハンダ付けする。続いてベース、エミッタのアル
ミニウムワイヤ８．９のボンディングを行い、ケース２
を接着剤でベース板Ｉに貼付けた後、チップとアルミニ
ウム保護のためシリコンゲル１０を注入する。このとき
ケース２の４隅の内側をＲ（アール）にしていない場合
は、上記従来装置のようにシリコンゲルの表面張力によ
り、ケース２の上部にまでシリコンゲル１０がはい上が
り、その後のエポキシ樹脂による封止のときにケース２
とエポキシ樹脂１）との接着が悪くなり、耐湿に関して
も悪い結果となることとなるが、このようにＲ部を設け
たことによりこの問題は完全に解消される。In FIG. 1, an insulating substrate 3, an emitter electrode 4, and a base electrode 5 are placed on a base plate 1, and a silicon chip 7 is placed on the base plate 1 in advance by high-temperature soldering on a molybdenum plate 6. , and solder at the same time using low-temperature soldering. Next, bond the base and emitter aluminum wires 8.9 and attach case 2.
is attached to the base plate I with adhesive, and then silicone gel 10 is injected to protect the chip and aluminum. At this time, if the insides of the four corners of the case 2 are not rounded, the surface tension of the silicone gel causes the silicone gel 10 to crawl up to the top of the case 2, as in the conventional device described above, and the subsequent epoxy resin Case 2 when sealed by
The adhesion between the epoxy resin 1) and the epoxy resin 1) will be poor, and the moisture resistance will also be poor, but by providing the R portion in this manner, this problem is completely resolved.

また第３図の本発明の他の実施例のように、ケース内側
の４隅にＲ（アール）部を設け、さらにこのＲ部の中間
にリブ３０を設けるとシリコンチップ）はい上がりは完
全になくなり、さらに効果は大きくなる。Furthermore, as in the other embodiment of the present invention shown in FIG. 3, if R (R) parts are provided at the four corners inside the case, and a rib 30 is further provided in the middle of the R part, the silicon chip (silicon chip) will not be able to rise completely. It disappears, and the effect becomes even greater.

なお、上記アール部あるいはリブはケース成形時に同時
に加工すれば、ケースの価格の上昇を招くことはない。Note that if the rounded portion or rib is processed at the same time as the case is molded, the price of the case will not increase.

なお、上記実施例は、１素子入りトランジスタモジュー
ルの場合番７ついて説明したが、本発明は多素子入り電
力用モジコールの樹脂封止形ケースにも適用でき、同様
の効果を奏する。In the above embodiment, case No. 7 of a one-element transistor module has been described, but the present invention can also be applied to a resin-sealed case of a multi-element power module, and the same effects can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、ケースの４隅にＲ（
アール）部を設けるか、またはケースの４隅の中間高さ
位置にリブを設けるようにしたので、ゲルのはい上がり
を防止でき、ケースとエポキシ樹脂との接着が良好とな
る効果がある。As described above, according to the present invention, the four corners of the case are provided with R (
By providing rounded portions or ribs at mid-height positions at the four corners of the case, it is possible to prevent the gel from creeping up and to improve the adhesion between the case and the epoxy resin.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例により半導体装置の平面図、
第２図は上記実施例のベース板に貼付けたケースの断面
図、第３図は本発明の他の実施例のケースの断面図、第
４図および第５図は従来の半導体装置の平面図および断
面図である。 １はベース板、２はケース、３は絶縁基板、４は千ミッ
タ電極、５はベース電極、６はモリブデン板、７はシリ
コンチップ、８はベースアルミニウムワイヤ、９はエミ
ッタアルミニウムワイヤ、２０はＲ（アール）部、３０
はリブ。 なお図中同一符号は同・−又は相当部分を示す。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a case attached to the base plate of the above embodiment, FIG. 3 is a sectional view of a case of another embodiment of the present invention, and FIGS. 4 and 5 are plan views of a conventional semiconductor device. and a cross-sectional view. 1 is a base plate, 2 is a case, 3 is an insulating substrate, 4 is a millimeter electrode, 5 is a base electrode, 6 is a molybdenum plate, 7 is a silicon chip, 8 is a base aluminum wire, 9 is an emitter aluminum wire, 20 is R (R) Department, 30
is rib. Note that the same reference numerals in the figures indicate the same, - or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] （１）金属ベース板上に絶縁層または絶縁基板を設け、
その上に電極板、半導体チップを順次ハンダ付けしこれ
をケースに収容してシリコーンゲル及び樹脂を用いて樹
脂封止を行う半導体装置において、 上記ケースの一部分に上記シリコーンゲルのはい上がり
防止部を設けたことを特徴とする半導体装置。(1) Providing an insulating layer or an insulating substrate on a metal base plate,
In a semiconductor device in which an electrode plate and a semiconductor chip are sequentially soldered thereon, the soldered product is housed in a case, and the silicone gel is resin-sealed using silicone gel and resin. A semiconductor device characterized in that: （２）上記はい上がり防止部は、上記ケースの４隅に設
けたアール部であることを特徴とする特許請求の範囲第
１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the crawling prevention portions are rounded portions provided at four corners of the case. （３）上記はい上がり防止部は、上記ケースの４隅内面
の中間高さ位置にその表面から突出して設けたリブであ
ることを特徴とする特許請求の範囲第１項又は第２項記
載の半導体装置。(3) The crawling prevention portion is a rib provided at an intermediate height on the inner surface of the four corners of the case so as to protrude from the surface thereof. Semiconductor equipment.
JP60245113A 1985-10-31 1985-10-31 Semiconductor device Granted JPS62104145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60245113A JPS62104145A (en) 1985-10-31 1985-10-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60245113A JPS62104145A (en) 1985-10-31 1985-10-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62104145A true JPS62104145A (en) 1987-05-14
JPH0418468B2 JPH0418468B2 (en) 1992-03-27

Family

ID=17128814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60245113A Granted JPS62104145A (en) 1985-10-31 1985-10-31 Semiconductor device

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JP (1) JPS62104145A (en)

Cited By (9)

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US6001943A (en) * 1997-01-30 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition and silicone gel for use in sealing and filling of electrical and electronic parts
US6001918A (en) * 1997-07-10 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition for use as a sealant and a filler for electrical and electronic components and a gel prepared from this composition
US7091580B2 (en) 2003-11-19 2006-08-15 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
WO2015111409A1 (en) 2014-01-27 2015-07-30 Dow Corning Toray Co., Ltd. Silicone gel composition
WO2018056297A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Curing reactive silicone gel and use thereof
WO2018056298A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Laminate, manufacturing method thereof, and manufacturing method of electronic component
WO2018079678A1 (en) 2016-10-31 2018-05-03 東レ・ダウコーニング株式会社 Layered body and method for manufacturing electronic component
WO2019049950A1 (en) 2017-09-11 2019-03-14 東レ・ダウコーニング株式会社 Cured silicone elastomer having radical reactivity and use of same
US11396616B2 (en) 2017-04-06 2022-07-26 Dow Toray Co., Ltd. Liquid curable silicone adhesive composition, cured product thereof, and use thereof

Citations (2)

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JPS56167552U (en) * 1980-05-15 1981-12-11
JPS58121652A (en) * 1981-12-11 1983-07-20 Fuji Electric Co Ltd Hybrid integrated circuit device

Patent Citations (2)

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JPS56167552U (en) * 1980-05-15 1981-12-11
JPS58121652A (en) * 1981-12-11 1983-07-20 Fuji Electric Co Ltd Hybrid integrated circuit device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001943A (en) * 1997-01-30 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition and silicone gel for use in sealing and filling of electrical and electronic parts
US6001918A (en) * 1997-07-10 1999-12-14 Dow Corning Toray Silicone Co., Ltd. Silicone gel composition for use as a sealant and a filler for electrical and electronic components and a gel prepared from this composition
US7091580B2 (en) 2003-11-19 2006-08-15 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
CN1307712C (en) * 2003-11-19 2007-03-28 株式会社丰田自动织机 Semiconductor device
US10155852B2 (en) 2014-01-27 2018-12-18 Dow Corning Toray Co., Ltd. Silicone gel composition
WO2015111409A1 (en) 2014-01-27 2015-07-30 Dow Corning Toray Co., Ltd. Silicone gel composition
WO2018056297A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Curing reactive silicone gel and use thereof
WO2018056298A1 (en) 2016-09-26 2018-03-29 東レ・ダウコーニング株式会社 Laminate, manufacturing method thereof, and manufacturing method of electronic component
KR20190046997A (en) 2016-09-26 2019-05-07 다우 코닝 도레이 캄파니 리미티드 LAMINATE, METHOD OF MANUFACTURING THE SAME,
KR20190051022A (en) 2016-09-26 2019-05-14 다우 코닝 도레이 캄파니 리미티드 Curing reactive silicone gel and uses thereof
US11279827B2 (en) 2016-09-26 2022-03-22 Dow Toray Co., Ltd. Curing reactive silicone gel and use thereof
WO2018079678A1 (en) 2016-10-31 2018-05-03 東レ・ダウコーニング株式会社 Layered body and method for manufacturing electronic component
KR20190080912A (en) 2016-10-31 2019-07-08 다우 도레이 캄파니 리미티드 Laminate and electronic component manufacturing method
US10961419B2 (en) 2016-10-31 2021-03-30 Dow Toray Co., Ltd. Layered body and method for manufacturing electronic component
US11396616B2 (en) 2017-04-06 2022-07-26 Dow Toray Co., Ltd. Liquid curable silicone adhesive composition, cured product thereof, and use thereof
WO2019049950A1 (en) 2017-09-11 2019-03-14 東レ・ダウコーニング株式会社 Cured silicone elastomer having radical reactivity and use of same
US11981814B2 (en) 2017-09-11 2024-05-14 Dow Toray Co., Ltd. Cured silicone elastomer having radical reactivity and use of same

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