JPS62102348A - Shared input/output system - Google Patents

Abstract

PURPOSE:To increase the number of CPUs which share input/output equipment and to reduce the size of hardware by connecting the respective CPUs to a common high-speed serial bus which is branched from system control buses of the plural CPUs through interface devices. CONSTITUTION:The interface devices 51-1-51-3 are connected to the system control (SC) buses 41-1-41-3 of the CPUs 40-1-40-3 respectively. Then, the interface devices 51-1-51-3 are connected to the high-speed serial (S) bus 61 in common and decentralized processors (DCP) 71-73 which control unshown input/output equipment are connected to this S bus 61. Consequently, the CPUs 40-1-40-3 share the input/output equipment through the corresponding interfaces 51-1-51-3, common S bus 61, and DCPs 71-73, so even if the number of the CPUs increases, the DCPs need not be altered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a shared input/output system in which a plurality of CPUs share an input/output device.

[Technical Background of the Invention] Generally, in a system consisting of a plurality of CPUs, expensive input/output equipment and equipment serving as a key station are often shared by each CPU. Figure 4 shows such a system, for example, three CPUs 1o-1~
10-3 is a system control bus (hereinafter referred to as SC bus) for the CPUs 10-1 to 10-3.
-i to 11-3, a distributed processing processor (hereinafter referred to as DCP) for controlling input/output equipment, and a bus switching module (hereinafter referred to as BSW) 3 via 21-1 to 21-3.
Connected to 0. BSW30 has CPU 10
For example, three common output buses 31-1 to 31-3 are provided for data input/output between -1 to 10-3 and input/output devices.
Selectors 32-1 to 32-3 are provided correspondingly.

CPIJlo-i (i = 1 to 3) is an input/output bus to which the target input/output device is connected, for example, input/output bus 3.
When attempting to acquire the right to use 1-1, a request to that effect is issued to the corresponding selector 32-1. The selector 32-1 is
If the input/output bus 31-1 is not used by another CPU, the bus 31-1 is
It is switched and connected to the DCP 21-i on the P U 10-i side.

This allows the CPU 10-i to use the input/output devices connected to the input/output bus 31-1.

[Problems with Background Art] However, in the conventional system described above, there is a problem that the number of selectors increases as the number of shared person output buses increases.

Also, since the selector has a limit on the number of inputs, the connected CPU
There was a limit to the number of Furthermore, in the conventional system, since all CPUs and BSWs in the system are electrically (DC) connected, there is a problem in that a failure in one selector spreads to other selectors.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to provide a shared input device that can significantly improve the number of CPUs that can share input/output devices, reduce the amount of hardware, and improve reliability. The purpose is to provide an output system.

[Summary of the Invention] In the present invention, a common high-speed serial bus branching from the system control bus of a plurality of CPUs is set via an interface device, and the CPUs are interconnected by the same serial bus. A distributed processor for controlling input/output devices is connected to the serial bus, and each CPU shares the input/output devices via a corresponding interface, serial bus, and distributed processor. The interface device forms an interface between the system control bus and serial bus of the corresponding CPU, and receives input/output device usage rights acquisition requests transferred from the CPU's arithmetic control unit, as well as input/output commands from the system control bus. Once received, the instruction is transferred to the distributed processor via the serial bus. The distributed processing processor has a serial bus interface function, and when an input/output device usage right acquisition request is transferred from the interface device via the serial bus, it performs usage right setting control in response to the request, and executes input/output commands. is transferred, the input/output switch is controlled. This allows cpu
Data input/output between input/output devices is performed via a system control bus, an interface device, a serial bus, and a distributed processing processor.

[Embodiment of the Invention] FIG. 1 is a block diagram showing an embodiment of the invention, and 40-1 to 40-3 are CPUs (central processing units). CP IJ 40-1 to 40-3 SC bus (system control bus) 41-1 to 41-3,
AU (arithmetic control units) 42-1 to 42-3 and memory control units (hereinafter referred to as MU) 43-1 to 43-3 that constitute CP tJ 40-1 to 40-3
etc. are connected. Also, SC bus 41-1 to 41-3
Interfaces ll51-1 to 51-3 are connected to the .

The interface devices @ 51-1 to 51-3 are also connected to a high-speed serial bus (hereinafter referred to as S bus) 61. Interface device [51-i (i = 1 to 3
) is an interface between the SC bus 41-1 and the S bus 61, and has an SC bus control section and an S bus control section (both not shown). The S bus control unit of the interface device 51-1 performs error recovery procedures, such as HD LC (
Hiah 1level Data Link Con
trol) procedure. Also, S bus 61 is C8MA
This media access is based on the /CD method (completely distributed peer-to-peer protocol with stochastic contention avoidance means), and has a transmission speed of 10 Mbit/s using, for example, a single coaxial cable as a medium.

The S bus 61 (the coaxial cable that constitutes it) includes, for example, three devices that control one or more input/output devices (not shown).
DCPs (distributed processing processors) 71 to 73 are connected via transceivers (not shown). DCP
71 to 73 are, for example, R3232C.

Processors for controlling non-procedural terminals, high-performance graphic displays, printers, and plotters connected using line standards such as R3422, processors for supporting transmission procedures,
Furthermore, GP-I B (GeneralP urp
It is used as a support processor for equipment connected to the ose-1nterface B LIS>.

The DCPs 71 to 73 have an S bus control section having an interface capability of the S bus 61 and an input/output device control section (none of which are shown). The S bus controllers of the DCPs 71 to 73 have procedures for error recovery, such as HDLC procedures.

Next, the operation of one embodiment of the present invention will be described with reference to the sequence charts of FIGS. 2(a) to 2(C), taking as an example the case where cpu 40-1 uses a desired input/output device. explain.

When the CPU 40-1 (A IJ 42-1') wants to use an input/output device, in order to obtain the right to use it, it first enters the address (channel number) of the DCP that controls the target input/output device, for example, DCP 71. and the address of the target input/output device (here, D that controls the target input/output device)
M U in CP IJ 40-1
43-1 storage area. Next, the A U 42-1 issues a command called "Oven" that includes information specifying the device list storage area, and sends the command to the interface device 51 via the SC bus 41-1 as shown in FIG. 2(a).
Transfer to ~1.

Upon receiving the oven command from the SC bus 41-1, the interface device 151-1 (the SC bus control unit, not shown) executes the oven command via the SC bus 41-1 according to the device list storage area specification information included in the command. M Ll 4
Access 3-1 and read the specified device list.

The interface device 51-1 then stores the device list read from the MU 43-1 in a storage unit (not shown) within the GL device 51-1.

Next, the interface device 51-1 (S bus control unit, not shown) is set in the device list (SC bus 4
1-1) converts the DCP address and input/output device address into an address compatible with the S bus 61.

Then, using the converted address, the interface device 51-1 identifies the DCP specified in the device list (here, DCP71) that is under the control of the DCP, as shown in FIG. 2(a). A command called command session start, which determines whether or not the target input/output device is usable (in this case, requests acquisition of the right to use the target input/output device), is transferred via the S bus 61. This command is issued sequentially for each input/output device specified in the device list.

When the DCP 71 (S bus control unit, not shown) receives a command session start command transferred from the interface device 51-1 via the S bus 61, it enables the use of the input/output devices specified by the command. It is determined based on the status of the input/output device, etc., and a positive response (response session start positive) or a negative response (response session start negative) is sent as shown in Figure 2 (a). Interface device 51
Returns -1. At this time, the DCP 71 displays CPU and input/output device correspondence information indicating that the requesting CPU can exclusively use the doujin output-like device if the input/output device specified in the command session start command can be used. Set in an undisclosed storage area. As a result, a logical bus called a session is established between the CPU that issued the oven command (here, CPU 40-1) and the available input/output devices.

The interface device 51-1 (S bus control unit) is
DCP6 for command session start command
When a response from 1 is received, information indicating whether or not the target input/output device can be used is set in the storage unit according to the content of the response (it is also possible to set it in the corresponding area of the device list). ).

Then, the interface device 51-1 repeatedly issues the command session start command for the input/output devices specified in the device list, thereby issuing the input/output devices requested by the CPU 40-1 (the AU 42-1 of the CPU 40-1). A list of devices that can be used is created in the storage section.

If all responses from the DCP 71 to the command/session/start command of the input/output device valve specified in the device list are positive responses, the interface device 51-1 (the SC bus control unit of the CPU 40) −
When a session is established between CPU 1 and all input/output devices requested by CPU 40-1, Cp
Notify AU 42-1 of U3O-1 of normal completion (for oven command). If there is a negative response even once because another system (in this case, CPU 40-2.4O-3) is in use, there is an input/output device that cannot establish a session with CPU 40-1. If even one exists, the interface device 51-1 is
Notify U 42-1 of error termination. In this case A
U 42-1 issues a status read command to interface device 51-1 to check for unavailable input/output equipment.

When the above oven command processing is completed, CPIJ
40-1 (AU42-1) issues an input/output command to the target input/output device that can be used as necessary, and as shown in FIG.
As shown in b), the data is transferred to the interface device [51-1] via the SC bus 41-1. This input/output command includes a DCP that controls the target input/output device, for example, DCP 71.
address, read or write control specification information for the doujin output device.

When the interface device 51-1 receives an input/output command from the CPU 401, the interface device 51-1 checks in the storage unit whether a session is set between the input/output device specified by the command and the CP tJ 40-1. Determined based on the setting information. If the target session is not set, that is, if the target input/output device is unavailable, the interface device 51-1 sends an error notification to the CPU 40-1 in response to the input/output command from the CPU 3O-1. Reply to. On the other hand, if the target session is set, that is, if the target input/output device is usable, the ink face device 51-1 determines whether read or write is specified. If read is specified, the interface device 51-1 sends only input/output commands to the S bus 61.
DCP71 (DCP that controls the target input/output device)
and wait for the data from the input/output device to be returned by the DCP 71. If write is specified, the ink face device 51-1 retrieves data from the storage area in the MU 40-1 specified by the input/output command from the CPU 40-1, and sends the same data along with the input/output command. The data is then transferred to the DCP 71.

When the DCP 71 receives an input/output command from the S bus 61, it decodes the command and controls the designated extraction saw device according to the decoding result. When the DCP 71 completes the input/output processing specified by the input/output command, it notifies the interface device 51-1 of this through the S bus 61, as shown in FIG. 2(b). Interface 1151-1
I) Upon receiving the input/output processing completion notification from CP7+,
As shown in FIG. 2(b), the completion of processing for input/output commands is sent to the CPU 4O-1 (AU4) via the SC bus 41-1.
2-1).

(:, p When A U 42-1 of IJ 40-1 finishes using the target input/output device, it releases the right to use the same device in the same manner as in the case of oven command issue 1:r. The command called close command is shown in Figure 2 (C
), the data is sent to the interface H location 51-1.

The interface device 51-1 is the cpu 40-1
When receiving a close command from the CPU 40-1, a command is issued to release the right to use the input/output device specified by the command, that is, to disconnect the session between the output device and the CPU 40-1. (Command session end command) is repeatedly transferred to the DCP 71 via the S bus 61 for the designated input/output devices (as in the case of the command session start command).

Upon receiving the command/session end command from the interface device 51-1, the DCP 71 disconnects the session set between the input/output device specified by the command and the CPU 41-1. , release the right to use the doujin output device from Cp IJ 40-1. As a result, CP IJ 40-2.42-3 is C; PL
l Obtaining the right to use the input/output equipment released from 4071 (
It becomes possible to

To disconnect the above session, connect the specified input/output device to cpU.
This is possible by deleting (or making invalid) the CPU and input/output device correspondence information indicating that 40-1 can be used exclusively.

When the DCP 71 performs session disconnection, the process shown in Fig. 2 (
As shown in C), a response (response session end positive) is returned to the interface device f&51-1. As a result, the interface device 51-1 is set in the storage section within the device 51-1 (CPU
4O-1) Delete information on the relevant input/output sensor from the usable input/output device list.

Now, in this embodiment, if a certain CPU goes down while having the right to use the input/output equipment.

Furthermore, other CPUs have usage rights! Il! If you want to use an input/output device in an emergency, you can use a method called forced oven to take away the right to use the input/output device. Strong control over the right to use this input/output device! Regarding profit, Part 3
This will be explained with reference to sequence chart 1 in the figure.

For example, in a state where the CPU 40-1 has acquired the right to use the input/output equipment connected to the DCP 71, the CPU 40-1
It is assumed that 40-3 wants to forcibly acquire the right to use the doujin output device. In this case, Cp U 40-3 is D C
A forced oven command requesting forcible acquisition of the right to use the target input/output device connected to P71 is sent to the SC bus 4 (in the same manner as when issuing a normal oven command).
1-3 to the interface Vt location 51-3.

When the interface device 51-3 receives a forced oven command from the CPU 40-3, the interface device 51-3 executes the DCP (here, DCP7
1), a command is transferred via the S bus 61 to the command session star 1 requesting forcible acquisition of the right to use the target input/exit device under control of the DCP (forced oven). Whether this command is a normal oven command (requesting input/output device usage rights 11q corresponding to a normal oven command) or a forced acquisition request (forced oven command) as in this example depends on the command. indicated by a specific field.

D CP 71 is an interface device jli5? -1 to the command session transferred via the S bus 61.
If the start command specifies a forced oven, the session that has already been set between the input/output device specified by the same command and the CPU 40-1 will be disconnected, that is, the corresponding CPU, input/output σI device correspondence information) and sends a notification to that effect (to command session 7 baud 1) to the interface device 51-1.

As a result, the interface device 51-1 deletes the corresponding input/output device from the list of available input/output devices and sends the response (response session appointment 1~ positive) to D.
Return to CP71.

Next, the DCP 71 transfers the input/output that was requested to be forcibly acquired to the device and C.
P1. , l40-3,
An affirmative response (response session star 1 - positive) to the command session start command is returned to the interface device 51-3.

As a result, the interface devices 51 to 3 add the corresponding input/output device to the list of available input/output devices.

As described above, it becomes possible to forcibly acquire the right to use the input/output device. Therefore, even if a failure occurs in any of the multiple CPUs, the Ike CPU can control the input/output rm device.
Improves system reliability.

In addition, in the embodiment, the S bus 61 is CSMA,
, .'Although the description has been made assuming a CD type serial bus, a token type bus is also applicable.

[Effects of the Invention] As described in detail above, according to the present invention, the following effects can be achieved.

■ System control 1-roll bus (SC) for multiple CPUs
A common bus that branches off from the bus is set up via an interface device, and each CPU is interconnected using the common bus, and the same bus is used for input/output device switching and control.
Minute 13H for 11! 1 Connecting physical processors (DCPs): By creating a hierarchical structure in Unahas, each CPU shares input/output devices via a corresponding ink space, a common bus, and a distributed processing processor. , C.P.
Even if the number of U increases, unlike conventional systems using bus switching modules, there is no need to make any changes to the input/output switching 1lIII (distributed processing processor).
The number of U units connected can be greatly improved and the amount of hardware can be reduced.

■ Since the serial bus is applied to the above common bus, the distributed processing processor is connected to the coaxial cable that constitutes the serial bus while being isolated from the processor by the 1-transceiver, so one distributed processing Processor failures do not spread to other distributed processing processors, improving reliability.

(2) Since a serial bus is used as the above-mentioned common bus, even if the number of CPUs increases, there is almost no increase in the number of cables, and therefore costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a practical example of the present invention, FIGS. 2(a) to 3(C) and 3 are sequence charts 1-1 for explaining the operation, and FIG. 4 is a conventional example. FIG. 40-1~4O-3-CPU, 41-1~41-
3-...System control bus (SC bus),
42-1 to 42-3... Arithmetic control unit f (AU)
, 51-1 to 51-3... interface device, 6
1... Serial bus (S bus), 71-73... Distributed processing processor (DCP). Applicant's Representative Patent Attorney Takeshi Suzue Gusaku Figure 1 (a) Figure 2 Iridonaberi (b) Seshi 4 Lighting Figure 2

Claims (2)

[Claims] (1) A high-speed serial bus and a device that has an interface function for this serial bus and performs usage rights setting control in response to input/output device usage rights acquisition requests from multiple CPUs transferred via the same serial bus, and the usage rights are acquired. A distributed processing processor that controls input/output devices according to input/output instructions from the CPU, and a corresponding CPU provided for each of the above CPUs.
It forms an interface between the system control bus of the CPU and the serial bus, and sequentially distributes the input/output device use right acquisition requests and input/output instructions transferred from the arithmetic control unit of the CPU via the system control bus via the serial bus. an interface device for transmitting data to a processing processor, and the serial bus branches from the system control bus of each of the CPUs via the corresponding interface device.
A shared input/output system characterized in that the CPUs are interconnected to share the input/output device via the distributed processing processor connected to the serial bus. (2) When the CPU requests forced acquisition of the right to use an input/output device, the interface device transfers the forced acquisition request to the distributed processing processor via the serial bus, and performs the distributed processing that received the forced acquisition request. 2. The shared input/output system according to claim 1, wherein the processor is configured to reset the right to use the input/output devices.