JPS62101112A - Sampling frequency conversion circuit - Google Patents

Abstract

PURPOSE:To attain asynchronous sampling frequency conversion by addressing a series of coefficient set of a coefficient table memory periodically, applying the operation between the coefficient set and an input sample string so as to obtain an output sample value. CONSTITUTION:A counter 2 counting a clock pulse synchronously with a timing pulse in an input sampling frequency fx and forming a series of addressed periodically is provided. A series of coefficient set written in a coefficient table memory 5 is designated sequentially by the address. A digital filter 4 or an operation circuit such as a polynomial interpolation operating circuit uses one of the coefficient set subject to address designation at each output timing in response to an output sampling frequency to apply operation to an input sample string thereby introducing an output sample value. It is not required to measure the time difference of the sample point between the input and the means as to each sample point and the accurate operation of the sampling frequency conversion is expected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for converting the sampling frequency of a digitized analog signal.

[Summary of the invention]

A series of coefficient sets in the coefficient table memory are periodically addressed with a series of addresses generated in the input sampling period, and an operation is performed between one coefficient set specified and the input sample sequence at a timing corresponding to the output sampling frequency. The system is configured so that the output sample value is obtained by applying the input signal to the output sample point, thereby making it possible to perform asynchronous sampling frequency conversion without measuring the individual time differences between the input and output sample points.

[Conventional technology]

FIG. 8 shows a sampling frequency conversion circuit disclosed in Japanese Unexamined Patent Publication No. 57-115015, and FIG. 9 shows a time chart of input and output sample sequences.

This sampling frequency conversion circuit basically uses a counter to find the time difference between the sampling timings of the input and output, converts the time difference information into a multiplication coefficient for the digital filter, and changes the sampling rate of the input sample string in the digital filter. I am getting an output sample sequence. That is, first, a timing pulse with an input sampling frequency fX is supplied to the PLL circuit 1 to generate a sufficiently multiplied clock pulse, and this clock pulse is counted by a counter 2 to calculate the input sampling frequency fX and the output sampling frequency f, Measure the start/stop time difference determined by each timing pulse. The measured time difference information φ5, that is, the time difference corresponding to the shift between the input sample point and the output sample point is sent to the time difference-coefficient conversion circuit 3, and a multiplication coefficient corresponding to the time difference is derived. Using this multiplication coefficient, the digital filter 4 convolves the sample sequence and outputs the sample value at the output sample point.

[Problem that the invention seeks to solve]

In the conventional circuit shown in FIG. 8, since the counter 2 frequently repeats start and stop, counting errors are likely to occur.
There is a problem in that the sampling rate cannot be converted reliably.

In view of this problem, it is an object of the present invention to eliminate the need to measure the time difference between human output timings and to perform reliable sampling rate conversion using simpler circuit means.

[Means for solving problems]

As shown in the embodiment of FIG. 1, a counter 2 is provided which counts clock pulses synchronized with timing pulses of an input sampling frequency fX to periodically form a series of addresses. A series of coefficient sets written in the coefficient table memory 5 are sequentially designated by the above address. An arithmetic circuit such as a digital filter 4 or a polynomial interpolation arithmetic circuit performs an arithmetic operation on the input sample string using one of the addressed coefficient sets at each output timing corresponding to the output sampling frequency and outputs the result. Derive sample values.

[Effect]

It is not necessary to measure the time difference between the sample points of the input and the means for each individual sample point, and circular addressing of the coefficient memory and one of the addressed coefficient sets is possible.
By extracting one, a set of coefficients can be obtained according to the time difference. The operation of address counter 2 at the input end is very stable as it does not repeat start and stop.
As a result, accurate operation of sampling frequency conversion can be expected.

〔Example〕

FIG. 1 is a block diagram of a sampling frequency conversion circuit showing one embodiment of the present invention. In the present invention, without measuring the time difference between the sampling points of the input and the output, the coefficient table memory stores the calculation coefficients of the filter corresponding to the time difference, and a series of coefficients are stored in relation to the input sampling timing. The configuration is such that the coefficient set can be addressed periodically, and further, one coefficient cent determined by the output sampling timing is used to perform an operation on the input sample string to obtain the output sample value.

In FIG. 1, a timing pulse with an input sampling frequency f is frequency-multiplied by a PLL circuit 1 and then applied to a counter 2 as a clock pulse. When the sampling rate conversion ratio is L/M (L, M: integers), the multiplication rate of the PLL circuit 1 is set as follows. The counter 2 has a full count value of L, and performs cyclic counting between count values O to L.

The cycle counting period is the frequency f of the input timing pulse
It is determined by X, and the output sampling frequency f.

The timing pulses are all (asynchronous).

The output of the counter 2 is used as an address pointer for the coefficient table memory 5.
address decoder 5a. The coefficient table memory 5 calculates the cent of the multiplication coefficient to be given to the digital filter 4 at the subsequent stage based on the time difference φ between input and output timings. , φ1/shi, φ2/L1φ3/L, -1--...---φ(L-
11/L is stored. The address pointer created by the output of the counter 2 is the address φ corresponding to the time difference between these times in the period of the input timing pulse. ,
φI/L −−−−−−−·−−−1−−···− are specified in sequence. Since the counter 2 repeats cyclic counting, addressing is also repeated cyclically. The full count value of counter 2 matches the total number of address pointers.

From the coefficient table memory 5, 1 necessary for filter calculation is
Coefficient data for cents is output simultaneously (in parallel) for each address specification. The read coefficient data is led to the digital filter 4 through the output sofa 6.

The output buffer 6 is of tri-state type and has an output sampling frequency f.

It becomes conductive with a timing pulse corresponding to . This timing pulse is also given to the digital filter 4 as a calculation start signal. Therefore, when the output side timing pulse is generated, the coefficient set specified by the address pointer at that time is taken into the digital filter 4. In the digital filter 4, a convolution operation or the like is performed on the input sample sequence using this coefficient cent, and an output sample value is calculated and derived.

Next, the coefficient sets in the coefficient table and the calculation procedure will be explained with reference to FIGS. 2 to 4. FIG. 2 is a time chart of input and output sample sequences, and FIG. 3 is an impulse response graph of the low-pass filter characteristics given to the digital filter 4. Further, FIG. 4 shows the frequency spectra of the input sample string and the output sample string.

If the sampling rate conversion ratio is L/M (L, M: integers), then in the digital filter 4, first the second
As shown in the figure, samples having L-1 zero values are interpolated between each sample of the input sample sequence (x4). In this example, L/M=415 and L-1=3 zero values are interpolated. Due to this zero value interpolation process (oversampling), the spectrum of the input sample sequence (xl) as shown in FIG. Lf, ). Note that the spectral distribution itself of the signal components of the input sample sequence is preserved without changing.

Next, in the digital filter 4, as shown in FIG. 4C, a low-pass filter process is performed to pass a signal band having a lower input or output sampling frequency (in this example, f, or <f) in a band below Lfx/2. I do. The low-pass filter characteristic may be one that shows an impulse response as shown in Figure 3, and the discrete amplitude value of this response characteristic is 0...-----.
・−・−−−−−−k , −・−・・・−・・−・−
By convolving kZr with the input sample sequence (x, 1) as a calculation coefficient sequence, a sample sequence interpolated for L times the number of sample points having a spectrum as shown in FIG. 4C is obtained. If you perform thinning processing to reduce the number of samples to 1/M for the sample string (115 in this example, outputting 1 out of 5 samples),
As shown in the fourth diagram, the sampling frequency is fy (
An output sample sequence (y, ) converted into L/MfX=415 f, ) is obtained.

Note that the above-mentioned convolution operation does not need to be performed on all sample points of the zero-value interpolated L-times sample sequence, but is performed on each sample point corresponding to the output sample sequence (yj) shown in Figure 2. That's fine. Therefore, the number of arithmetic circuits can be reduced to 1/M, and thinning processing is performed along with this arithmetic processing.

The coefficient sequence corresponding to the impulse response G of the low-pass filter characteristic is, for example, as shown in FIG.
k z , −−−−−−−−−・−−−−−−−k
r, kzt-r, kzr). The calculation operation for obtaining the output sample sequence (y,) by convolving the input sample sequence (X,) and the coefficient sequence (k,) can be expressed by the following equation.

y; ”−・−・・−−−−+ X 4− z ・k
(r4L-φjL> 9 for +xi-1', -φjL
) 1Xi ” +r-t-φjL) ”i+I
'k 1r-KL-φjL) ” −'-'-・
−・・−−−−m−−−−(φ, = 0/S, 1/L,
2/L, --------------・・−・−−・−1−−−
−・−・・−・−(L −1)/L) That is, the central coefficient k of the impulse response shown in FIG.

and the sample value X, -3 of the input sample sequence in Fig. 2 are superimposed, and the impulse response function is further calculated by the time difference φ, (2/L in this example) between the input sample point X1-1 and the output sample point y. With the input sample sequence (X,) shifted to the right, a product-sum operation is performed on the input sample sequence (X,) and the coefficient sequence (k,). X
The coefficient corresponding to l-1 is -φjL = k r-2
Then, the coefficient corresponding to X is kr-L-φjL = kr-2-4, which is L apart from kfr-φjLl. Similarly, every L-1 (every third) coefficient is subjected to a sum-of-products operation with the corresponding input sample sequence to obtain one output sample value yJ. In other words, since we know that the multiplication result is zero for zero values interpolated in the input sample sequence, we use a set of coefficients extracted every L-1 from the impulse response coefficient sequence. All you have to do is calculate.

The coefficient table memory 5 in FIG. 1 stores such coefficient sets based on the time difference φ between input and output. , φ18, φ2/L , -
−−−−−−−φ. -11/L are sequentially stored as shown in FIG.

Each coefficient cent is accessed by periodic addressing synchronized with the input timing pulse, and a corresponding set of coefficients is created when the output timing pulse occurs, depending on the time difference φ from the current input timing. will be selected.

Note that the output sample values can be obtained in the same manner by using a polynomial interpolation calculation block instead of the digital filter 4 in FIG. 1.

FIG. 6 is a block circuit diagram showing another embodiment of the present invention,
The output buffer 6 of FIG. 1 is arranged between the counter 2 and the coefficient table memory 5. As in FIG. 1, the counter 2 generates an address count output that periodically addresses the coefficient table, and the output buffer 6 outputs the count output to the coefficient table memory 5 in synchronization with the output timing pulse. Therefore, in this embodiment as well, the counter 2 performs cyclic counting, its output enables periodic addressing of the coefficient table memory, and the output timing pulse selects one of the coefficient cents. .

Next, FIG. 7 is a block circuit diagram showing yet another embodiment,
It has a configuration in which the basic circuit shown in FIG. 1 is connected in multiple stages. That is, a coefficient table memory 5 and an output sofa 6 are attached to each of the digital filters 4 having a multi-stage cascade configuration, and each memory 5 is periodically addressed by the output of a counter 2 that counts a clock obtained by multiplying an input timing pulse. . The timing circuit 7 has two types: one that controls the timing of the output vanofer 6 and the digital filter 4 depending on the input timing pulse or the output of the PLL circuit 1, and the other that controls these depending on the output timing pulse. Conceivable.

For example, when converting the sampling frequency from 48 kHz to 44.1 kHz, the conversion ratio is 147/1.
60, the necessary conversion ratio can be obtained by a cascade combination of digital filters 4 that perform oversampling and decimation such as 7X7X3÷8÷4÷5. In this case, the digital filter 4 that performs only oversampling operates in synchronization with the input timing pulse, and the digital filter 4 that performs thinning processing operates in synchronization with the output timing pulse.

In each of the embodiments described above, the counter 2 may have a jitter suppression function or may perform time averaging. Further, in each embodiment, the output cover sofa 6 and the digital filter 4 may be controlled based on a pulse obtained by multiplying or frequency-dividing the output sampling pulse. Furthermore, the sampling frequency conversion circuit shown in the embodiment is composed of a combination of functional blocks, and is composed of a digital signal processing processor each equipped with a ROM as a coefficient memory, a RAM as a sample data memory, a multiplier, and an accumulator. It can constitute the main part or the whole part.

〔Effect of the invention〕

As described above, the present invention uses the counter 2 to periodically generate addresses specifying a series of coefficient sets in synchronization with the input timing, and selects one of the coefficients at the output timing to match the input sample sequence. Since the calculation is performed, there is no need for the counter 2 to operate discontinuously (start/stop) in response to the time difference between input and output timings, and the coefficient set can be read out in continuous operation.
Therefore, very stable operation can be obtained and accurate sampling frequency conversion can be performed.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram of a sampling frequency conversion circuit showing an embodiment of the present invention, Fig. 2 is a time chart of an input sample sequence and an output sample sequence, and Fig. 3 is an impulse of low-pass filter characteristics given to a digital filter. Graph of the response, Figure 4 is the frequency spectrum of the input and output sample sequence, Figure 5 is the data arrangement diagram of the coefficient table, Figure 6 is a block circuit diagram showing another embodiment, Figure 7 is a multi-stage configuration. FIG. 8 is a block circuit diagram of a conventional sampling frequency conversion circuit, and FIG. 9 is a block circuit diagram of a conventional sampling frequency conversion circuit.
The figure is a time chart of the input and output sample sequences in FIG. In addition, in the symbols used in the drawings, 1-----------------PLL circuit 2
−−−−−・−−−−−−・−・−Counter 4−・−・
・・・−・−Digital filter 5−−−−−−−−
−−1・−・−Coefficient table memory 6・・・−・−−−
-------1--This is an output vanofa.

Claims (1)

[Claims] A counter that periodically forms a series of addresses by counting clock pulses synchronized with the timing pulse of the input sampling frequency, a coefficient table memory that sequentially specifies a series of coefficient sets according to the addresses, and a coefficient table memory that corresponds to the output sampling frequency. an arithmetic circuit that performs arithmetic operations on an input sample string using one of the addressed coefficient sets at each output timing to obtain an output sample value.