JPS62101035A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a contact hole, which has an inclination spreading toward an upper section and a lower section thereof takes the same dimensional shape as mask size, and to obtain a fine integrated circuit resulting in no disconnection of a wiring metal by implanting the ions of an impurity in high concentration to the contact hole section and executing RIE to the contact hole section. CONSTITUTION:A silicon oxide film through chemical vapor phase growth is deposited as an inter-layer insulating film 6 in order to insulate a gate electrode 5 and an aluminum wiring formed onto the gate electrode 5 and flatten the surface. A photo-resist 7 is applied onto the inter-layer insulating film 6, and patterning through which only a contact hole section is removed is conducted. Phosphorus ions are implanted only to the contact hole section, using the photo-resist 7 as a mask. RIE is performed, and etching speed is increased in the vicinity of the surface of the inter-layer insulating film 6, to which an impurity is doped in high concentration, and side etching is generated, but the bottom of the film 6 is etched to approximately the same pattern shape as the pattern shape of the resist, thus the contact hole 8 having sectional structure inclined so as to extend toward an upper section.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a contact hole with an upward slope is formed.

[Conventional technology]

Conventionally, contact holes were formed by etching the insulating film with a photoresist and using wet etching to remove the portions not covered by the photoresist using a chemical such as hydrofluoric acid.However, recent manufacturing processes With the miniaturization of patterns, reactive ion etching (IE) is becoming mainstream.

FIG. 3 is a sectional view of a contact hole formed by conventional wet etching, and FIG. 4 is a sectional view of a contact hole formed by IE.

[Problem that the invention seeks to solve]

Contact hole formation by conventional wet etching is
The edge of the insulating film under the mask material has a certain degree of inclination, which is advantageous for preventing disconnection of metal wiring formed on the insulating film, but etching also progresses in the lateral direction, making it difficult for microprocessing. do not have.

On the other hand, although a contact hole having approximately the same shape as the mask material can be obtained by RIE, the edges of the etched insulating film are steep, so that when a metal wiring is formed on this insulating film, disconnection may occur.

[Means for solving problems]

The second aspect of the present invention improves this prior art.

The present invention provides a manufacturing method for realizing a contact hole structure in which the bottom part of the contact hole, which is the connection part with the diffusion layer, has the same dimensions and shape as the mask mask, and has a slope that widens toward the top. be.

The method for manufacturing a semiconductor device of the present invention includes the steps of forming an insulating film on a semiconductor substrate, depositing a mask material on the insulating film, and removing a predetermined portion of the mask material to form an opening to fully expose the insulating film. After the formation process and ion implantation of impurities into this exposed insulating film.

The method is characterized in that it includes a step of etching.

〔Example〕

Next, the present invention will be explained using the drawings.

FIGS. 1(a) to 1(e) show an embodiment in which the present invention is applied to the manufacture of a silicon gate electric effect transistor.

FIG. 3 is a cross-sectional view of each manufacturing process from forming an interlayer insulating film to forming an aluminum wiring. A field oxide film 2 for isolation between elements is provided on the surface of a silicon substrate 1.

A silicon gate field effect transistor consisting of a gate oxide film 3, a source-drain diffusion layer 4, and a polycrystalline silicon gate electrode 5 is formed on the element formation region. The steps will be explained below in order.

First, a silicon oxide film (CVDSiOz) of approximately 1 μm is deposited by chemical vapor deposition as an interlayer insulating film 6 between the gate electrode 5 and the aluminum wiring formed thereon, and to flatten the surface. Figure 1(a)).

Then, a photoresist 7 is deposited on the interlayer insulating film 6 and patterned to remove the contact hole portion 6 (
UJ! Figure 1 (b)).

Using this photoresist 7 as a mask, phosphorus ions are implanted only into the contact hole. At this time, the dose of ion implantation is I x 10 ~ I x 1015m-"
(Figure 1 (C)).

Next, by performing Ig, the etching speed is high near the surface of the glabella insulating film 6 doped with a high concentration of impurities, causing side etching, but the bottom part is etched with a pattern shape that is almost the same as the pattern shape of the resist. As a result, a contact hole 8 having a cross-sectional structure t inclined upwardly is obtained (FIG. 1(d)).

After aluminum is deposited on the glabella insulating film 6 and on the contact hole 8, patterning is performed by a known method to form aluminum wiring. Here, the thickness of the aluminum wiring is about 1 μm, which is the same as the ff1fiJI insulating film, but since there is a slope above the contact hole, there is no disconnection at the contact hole portion.

〔Effect of the invention〕

As explained above, in the second aspect of the present invention, by performing RIE after ion-implanting high-concentration impurities into the contact hole portion, the contact hole has a slope that spreads toward the top, and the bottom portion has the same size and shape as the mask size. It has the effect of forming holes, making it possible to produce fine holes, preventing disconnection of wiring metal, and producing a collector circuit, thereby improving the yield of products.

2. In Example S, the formation of contact holes in the insulating film between the eyebrows between the diffusion layer and the metal wiring was explained, but in the multilayer wiring process 2, it is also effective for forming through holes in the interlayer insulating film between the wiring layers. Needless to say.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views of each manufacturing process according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a contact hole according to an embodiment of the present invention, and FIGS. 3 and 4. are cross-sectional views of contact holes formed by conventional wet etching and reactive ion etching, respectively. 1...Silicon substrate, 2...Field oxide film, 3...Gate oxide film, 4...
- North-drain diffusion layer, 5... polycrystalline silicon fist gate electrode, 6... interlayer insulating film, 7...
...Photoresist, 8...Contact hole, 9...Aluminum wiring. Agent Patent Attorney Susumu Uchihara District 1, District 3 Zumu 4 concave 2nd rooster

Claims (1)

[Claims] forming an insulating film on a semiconductor substrate; depositing a mask material on the insulating film and removing a predetermined portion of the mask material to form an opening through which the insulating film is exposed; 1. A method of manufacturing a semiconductor device, comprising the steps of ion-implanting impurities into a film and then etching the film.