JPS62100010A - Logarithmic amplifier - Google Patents

Abstract

PURPOSE:To obtain a stable amplified output by using a transistor (TR) so as to synthesize plural detection outputs whose amplitude is limited. CONSTITUTION:A high frequency signal impressed to an input terminal 1 is amplified sequentially by high frequency amplification circuits 2 connected in cascode by N stages. A detection circuit 3 is connected to each amplifier circuit 2 and a detection output in response to a level of the input signal is obtained at each stage. The detection outputs are subjected to amplitude limit by a video limit circuit 4 provided with an amplitude limit diode (not shown in a figure) and the result is inputted to a synthesis circuit 51. The synthesis circuit 51 consists of a common base TR 38 and a variable voltage source 39 and the output of the limit circuit 4 is given to the emitter of the TR 38. The voltage source 39 is connected to the base to supply a threshold value and a synthesis output is obtained from the collector. Thus, a stable amplified output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a successive detection waveform logarithmic amplifier having broadband characteristics and high speed.

[Conventional technology]

FIG. 4 shows, for example, U.S. Pat. No. 3,668,535 (gune
, 6, 197'2). In the figure, 1 is an input terminal for a high frequency (hereinafter referred to as RF) signal, and 2 is a wideband RF signal input terminal.
3 is a detection circuit, 4 is a video limiting circuit that limits the detection output j to a predetermined threshold value, 5 is a transmission line, 6 is a matching termination resistor, 7 is a load resistor RL, 5
1 is a synthesis circuit.

Next, the operation will be explained. RF applied to input terminal l
Sequential amplification is performed in the RF amplifier circuit 2 connected to the double signal cascode in N stages. Detection circuit 3 in parallel with each amplification stage
are connected, a detection output corresponding to the level of the input RF signal can be obtained at each stage. These detected outputs are amplitude limited by a video limiting circuit 4, and the signal outputs are synthesized by a transmission line 5 constituting a synthesizing circuit 51.

Since the transmission line 5 can be viewed as a kind of delay line, 11
π of continuous inductance 8 and parallel capacitance 9
It is shown as a type equivalent circuit. The purpose of this is to reduce waveform distortion by delay-synthesizing the RF false signal propagation delay generated in the RF amplifier circuit 2 with equal phase on this transmission line. The detected signal, which is synthesized while propagating through the transmission line 5, is supplied to the load resistor 7. In this case, the terminating resistor 6 on the input side is for matching the transmission line 5.

FIG. 5 shows the output characteristics of the logarithmic amplifier constructed in this way. The figure shows a case where an RF amplifier circuit with N=8 stages is used, and each stage has a dynamic range of 10 dB. First, the output of the 8th stage RF amplifier 2 is amplified by 80 dB, and the detection circuit 3 is made conductive to obtain a detection output.
As the input RF signal level increases, the detection output also increases almost linearly and finally reaches the peak of the video limit output.

Video amplitude limiting is performed on the transmission line 5. Approximately 10d
During the clean range of B, a detection output having a logarithmic characteristic similar to the level of the human RF signal is obtained.

In this way, as the input RF signal level increases, the detection outputs from the 8th stage to the 1st stage are sequentially advanced, so that in the transmission line 5, finally, 8 outputs are processed, as shown in FIG. An output characteristic of 10 is obtained.

FIG. 6 shows the realization of the above-mentioned contents as a concrete circuit. In FIG. 6, the RF amplifier circuit 2 uses a grounded emitter transistor 11. This transistor 11
A base bias is supplied from a power supply 12 via a power supply line 15 including a filter circuit consisting of an inductance 13 and a capacitor 14. Resistors 1G and 17 connected in series are for voltage division to provide the base potential of the L-transistor 11, and a capacitor 18 connected to the base side of the transistor 11 is connected to the RF false signal input terminal 11. It is for use. Further, a resistor 19 is connected between the emitter terminal of the transistor and the power supply line 15 to apply an appropriate bias current to the transistor 11. ] - The capacitor 20 connected to the emitter terminal of the transistor 1 is for RF false signal bypass, and the variable inductance 21 connected to the collector terminal of the transistor 11 determines the resonant frequency of the amplifier circuit together with the parasitic capacitance in the circuit. , for tuning the center frequency of the amplifier circuit 2, and RF
An inductance 22 and a resistor 23 connected between the input terminal 1 and the collector terminal of the transistor 11 are negative feedback elements that have the effect of widening the band by lowering the gain of the amplifier circuit, and are connected in parallel with the inductance 21. The resistor 24 is for interstage matching of about 100 ohms.

Further, the detection circuit 3 is connected to the collector terminal of the transistor 11. In the detection circuit, a detection diode 25 (for example, Schottky type) and a load resistor 26 are connected in series, and are bypassed by an RF false signal capacitor 27. The output of the detection circuit 3 is coupled by a capacitor 28 to a video limiting circuit 4, where it is connected to a forward biased diode 29. The limiter diode 29 allows a bias current to flow from the power supply line 15 through a high frequency choke 30 and a resistor 31.
Since this resistance value is very high, for example, on the order of 100 ohms, the current flowing through the diode appears to be receiving a bias current from a constant current source with infinite impedance. Therefore, fluctuations in the voltage drop caused by temperature changes in the limiter diode 29 can be ignored, and the high-pass current hardly changes, so the video limiting characteristics of the diode are also stable. This limiter diode 29 is connected in series between the detection circuit 3 and the transmission line 5, and a signal current is supplied to the load resistor 7RL.

The resistor 32 is used to provide isolation between the video limiting circuits 4, and has a value approximately 10 times that of the load resistor 7. A simplified Brookock diagram of the video limiting circuit is shown in FIG. Forward bias current Ib, as shown in the figure, includes load resistance RL, isolation resistance 32°, limiter diode 29.
and is flowing through the bias resistor 31. On the other hand, the signal current I51° is applied from the output of the detection circuit 3 to the equivalent resistance 33.degree. which is the output impedance. Limiter diode 29.
Isolation resistor 32. When o Ib = ts+c flowing through the load resistor -RL, the diode is reverse biased, so the current is limited, and no more signal current is supplied to the load.

As yet another embodiment, there is a circuit configuration shown in FIG. This figure is almost the same as the circuit described above except that the limiter diode 29 in the video limiting circuit 34 is connected in parallel with the load resistor 7. Specifically, in the detection circuit 3, a matching resistor 35 is connected in cascade to the detection output and the video limiting circuit 34.
There is also a difference. The video limiting operation is performed by forward biasing the limiter diodes 29.2, and this limited voltage is supplied to the load resistor 7. A simplified diagram of this is shown in FIG. The voltage generated in the detection circuit 3 is applied to the limiter diode through a resistor 36-, which is the sum of the internal impedance of the detector and the matching resistor 35. This diode is video-limited by the forward-biased voltage, and is also supplied to the load resistor at the same time.

The variable voltage power supply 37 shown in the video limiting circuit in the figure is an example in which the above-mentioned video limiting can be set arbitrarily without depending on the voltage drop caused by the diode.

[Problem that the invention seeks to solve]

In the case of a conventional logarithmic amplifier, the capacitor 28 cannot be omitted in the circuit shown in Fig. 6, so it cannot handle up to DC as the detection output, and sag occurs when the signal waits for a patented long pulse width in pulse compression radar etc. signal cannot be reproduced faithfully. Furthermore, in the case of continuous wave CW, there was a drawback that it could not be handled at all. However, in the circuit shown in FIG. 8, which was designed to compensate for this drawback, the video limit voltage fluctuates with temperature due to the temperature dependence of the forward voltage of the diode.
0% change is allowed. In this invention, by configuring the detection output with a directly connected circuit, it is possible to handle continuous wave input, and at the same time, by configuring the circuit to cancel out the temperature stability that occurs in this case, a logarithmic amplifier with good temperature stability is obtained. The purpose is to Furthermore, in the conventional method, the voltage excited in the transmission line 5 of the detection output was the immediate output voltage, so this voltage fluctuated depending on the input signal level, causing the video limit, which was originally supposed to be constant, to fluctuate. There was a drawback. In other words, in the example shown in FIG. 6, the voltage excited in the transmission line 5 is tried to be separated as much as possible by the isolation resistor 32 from the voltage excited by the detection output current: l5IG, but it is not perfect and the input terminal Since the closer the detector circuit is, the higher the video limit voltage becomes, so obtaining the input/output characteristics shown in FIG. 5 required a great deal of adjustment time and effort.

This invention also solves this problem by using a transistor with a grounded base, which allows stable video limiting.
Another purpose is to facilitate adjustment.

[Means for solving problems]

Therefore, the video limiting circuit according to the present invention includes a diode that is connected in series with the detector of the detection circuit and limits the amplitude of the detection output of the detection circuit at a predetermined threshold, and the combining circuit is The present invention is characterized in that it includes a transistor that supplies the threshold voltage of the video limiting circuit and synthesizes the detection output whose amplitude has been limited by the video limiting circuit.

[Effect]

The diode of the video limiting circuit according to the present invention limits the amplitude of the detection output of the detection circuit. Further, the transistor of the synthesis circuit according to the present invention synthesizes the detection outputs of the amplitude-limited detection circuits and supplies a threshold voltage for amplitude limitation.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention, with 38
39 is a grounded base transistor for synthesizing and adding detected output currents, and 39 is a variable voltage source that supplies a predetermined threshold voltage to the video limiting circuit through this transistor. Here, the base-grounded transistor 38 and the variable voltage source 39 constitute a composite circuit 51.

The difference from the conventional method in the figure is that the conventional method of combining detection outputs in the transmission line has been changed to a method of adding currents at the emitter and terminal terminals of the transistor 38 with the base grounded. The method of combining on the transmission line is
In the past, when RF amplifier circuits were narrowband circuits using vacuum tubes, etc., the group delay characteristics were large, so simply combining the detection outputs caused waveform distortion and lost high speed, so it was unavoidable. This is the method I was using. However, since semiconductor amplifiers with broadband characteristics are currently used, the delay characteristics are almost equivalent to the propagation distance, and in miniaturized circuits, there is no problem with high speed even if delay synthesis using transmission lines is not used. The base-grounded transistor 38 receives the detection output current ('I+'2·-1n-1) from the video limiting circuit 4.
+1n) is connected to the emitter terminal of the transistor to perform current addition (+1-Σik), which is output from the collector terminal 4 and converted into voltage by the load resistor R and 7 to obtain the detected composite output. . In the figure, I of the ground plane
- Although the transistor 38 is a PNP type transistor, an N P N type transistor may be used depending on the one-choice configuration.

A variable voltage source 39 connected to the base of the 1-transistor 38 not only provides bias for the transistor, but also provides a threshold voltage 5 to the video limiting circuit 4 via the 1-transistor terminal of the transistor. The voltage drop between the base and emitter of a transistor is normally about 0.65 V, and it hardly changes even when the current of addition current + it changes. The threshold voltage of the limiting circuit 4 does not fluctuate and is stable. Furthermore, since current synthesis can be performed at low impedance, the isolation resistor used conventionally can be omitted, and the maximum detection output can be extracted.

The circuit diagram shown in FIG. 2 realizes this in a concrete circuit. The difference between this figure and FIG. 6 is that the video limiting circuit has been improved and the combining circuit using transmission lines has been replaced with a combining circuit using 3 transistors. The modification of the video limiting circuit 40 is that of the conventional coupling capacitor 2.
8 is omitted and the current limiting resistor RA 41 is used instead of the isolation resistor 32. In order to explain this operation, a simplified block diagram is shown in FIG. In the figure, the bias resistor 31 is the detection diode 25.
Bias current: Ibl and limiter diode 2
9 video limiting currents 1b2 are flowing respectively,
As mentioned above, since the resistance value is sufficiently large, it can be considered as a constant current source. If there is no detection output, the detection voltage Va
"O, and the potential on the cathode side of the detection diode 25 is 0 volts because it is grounded by the high frequency choke 21. Also, the currents 1bl and Ib2 flowing through the detection diode 25 and the limiter diode 29 are almost the same. Therefore, the voltage drops Va+ and VaZ due to each diode are almost the same.Therefore, the cathode side potential of the limiter diode 29 is also the same as that of the detection diode 2.
Since the potential is the same as the cathode side potential of 5, and it is considered to be approximately O volts, the video limiting current Ibz=V/Rr. When the detection voltage V increases, the current flowing to the constant current source becomes t b+ + r bz-- From the constant principle, the current ■1
increases, current rbz decreases, and finally voltage V = voltage VL, current 1bz"0, and further voltage V,
>At voltage VL, the limiter diode 29 is reverse biased and the current is limited.

The NPN transistor 38 in FIG. 2 adds the video limiting current Ib2 output from the video limiting circuit 40. Limiter voltage V.

are a transistor 42 and a voltage dividing resistor 43 . whose bases face each other with the transistor 38 . ．． 14 is set at a potential obtained by dividing a reference voltage 2, which will be described later. Since the base and collector are directly connected, the transistor 42 is equivalent to a simple diode, and the current combining transistor 38
This is for compensation to cancel out the fluctuations caused by temperature in the base-emitter voltage Vbe of . Therefore, the emitter terminal of the current combining transistor 38 is at the same potential as the voltage drop caused by the voltage dividing resistor 44, and this voltage is the limiter voltage
The potential is almost constant. The added current it is converted into a voltage by a pseudo load resistor 45, and is supplied to a load resistor RL7 via an emitter follower type (grounded collector) transistor 46 and an output impedance matching resistor 47. At the same time, the resistor 47 and the resistor 48 also provide a bias for the transistor 46. The PNP transistor 49 has a reference voltage set by a variable resistor 50, which is determined via a resistor 51, and the above-mentioned transistor is Similar fluctuations of 38, 42 and 46 are offset to achieve direct current stabilization. Therefore, the variable resistor 50 sets the zero point potential of the output.

Note that in the above embodiment, transistors 42, 46 and 49
However, an integrated circuit such as an operational amplifier may also be used.

〔Effect of the invention〕

As described above, according to the present invention, the video limiting circuit:
The synthesis circuit is connected in series with the detector of the detection circuit and includes a diode for limiting the amplitude of the detection output of the detection circuit at a predetermined threshold, and the synthesis circuit supplies the threshold voltage of the video limiting circuit and Since it is equipped with a transistor that synthesizes the detected output whose amplitude has been limited by the above video limiting circuit, it can be configured with a direct connection circuit, and the video limiting voltage is stable regardless of the input level, and the mirror effect due to the feedback capacitance inside the transistor Since it is not affected by
It will also be possible to handle ultra-fast pulse signals of seconds.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a specific circuit diagram of the block diagram in FIG. 1, FIG. 3 is a simplified block diagram of a video limiting circuit, and FIG. 4 is a conventional A block diagram of the logarithmic amplifier, Fig. 5 is an output characteristic diagram of the logarithmic amplifier in Fig. 4, Fig. 6 is a specific circuit diagram of Fig. 4, and Fig. 7 is a simplified block diagram of the video limiting circuit in Fig. 4. , 8th
This figure is a specific circuit diagram showing another example of FIG. 4, and FIG. 9 is a simplified block diagram of the video limiting circuit in FIG. 8. 2 is a radio frequency (RF) amplifier circuit, 3 is a detection circuit, 4 is a video limiting circuit, 38 is a transistor, 39 is a voltage source for video limiting, and 51 is a combining circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa (2 idiots) PF L
NPUT LEVa [dBM) 37 2-electronic power 2. Name of the invention Logarithmic amplifier 3. Representative Moriya Shiki 5. Date of amendment order January 28, 1985 6. Amendment lil of the target drawings. 7. Contents of amendment (1) The drawings and all drawings shall be amended as shown in the attached sheet. Above procedures Amendment letter = (1) 6) 7.4
30 Showa month [j

Claims (1)

[Claims] A high frequency signal is sequentially amplified by a predetermined gain by a plurality of high frequency amplifier circuits connected in cascode, and the amplified high frequency signals are sequentially detected by a detection circuit connected in parallel with the high frequency amplifier circuit. In the logarithmic amplifier of the successive detection waveform, the amplitude of the detection output obtained from this detection circuit is limited by a video limiting circuit, and the amplitude-limited detection output is synthesized by a synthesis circuit to obtain an output with approximately logarithmic characteristics. The video limiting circuit is connected in series with the detector of the detecting circuit, and includes a diode that limits the amplitude of the detected output of the detecting circuit at a predetermined threshold, and the combining circuit includes a diode that limits the amplitude of the detected output of the detecting circuit at a predetermined threshold. A logarithmic amplifier comprising a transistor that supplies the threshold voltage of the circuit and synthesizes the detected output whose amplitude has been limited by the video limiting circuit.