JPS6199246U - - Google Patents
Info
- Publication number
- JPS6199246U JPS6199246U JP18481884U JP18481884U JPS6199246U JP S6199246 U JPS6199246 U JP S6199246U JP 18481884 U JP18481884 U JP 18481884U JP 18481884 U JP18481884 U JP 18481884U JP S6199246 U JPS6199246 U JP S6199246U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- control signals
- ary counter
- terminal
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の好適な一実施例を説明するブ
ロツク図、第２図は第１図の動作を説明する波形
図、第３図はデバツグ装置とプロトタイプとの関
係を示すブロツク図である。
図において、１０はデバツグ装置、１２はプロ
セツサ、２２はＮ進カウンタ、２４はデコーダで
ある。
FIG. 1 is a block diagram explaining a preferred embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing the relationship between the debugging device and the prototype. . In the figure, 10 is a debug device, 12 is a processor, 22 is an N-ary counter, and 24 is a decoder.
Claims (1)
御信号の授受を行なうプロセツサ用のデバツグ装
置において、上記プロセツサと同時にリセツトさ
れ、上記プロセツサの上記端子の制御信号を計数
するＮ進カウンタと、該Ｎ進カウンタの計数値を
デコードするデコーダとを具えたデバツグ装置。 In a debugging device for a processor that sends and receives N types of control signals (N is an integer of 2 or more) at a single terminal, an N-ary counter that is reset at the same time as the processor and counts the control signals at the terminal of the processor. and a decoder for decoding the count value of the N-ary counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984184818U JPH0337074Y2 (en) | 1984-12-05 | 1984-12-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984184818U JPH0337074Y2 (en) | 1984-12-05 | 1984-12-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6199246U true JPS6199246U (en) | 1986-06-25 |
| JPH0337074Y2 JPH0337074Y2 (en) | 1991-08-06 |
Family
ID=30742303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984184818U Expired JPH0337074Y2 (en) | 1984-12-05 | 1984-12-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337074Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6134636A (en) * | 1984-07-27 | 1986-02-18 | Yokogawa Hokushin Electric Corp | Dma detecting circuit of auxiliary processor |
-
1984
- 1984-12-05 JP JP1984184818U patent/JPH0337074Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6134636A (en) * | 1984-07-27 | 1986-02-18 | Yokogawa Hokushin Electric Corp | Dma detecting circuit of auxiliary processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0337074Y2 (en) | 1991-08-06 |
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