JPS6197916A - Method of exposure of wafer and its device - Google Patents

Abstract

PURPOSE:To prevent a double exposure from generating by covering this regis tration portion with such as a shutter through registering a part of pattern for being exposed hereafter on a scribe area or a chip of an exposure surface exposed already and by positioning. CONSTITUTION:After a chip 6 arranged in an exposure surface 3 is orderly arranged by providing a certain scribe area 7, an alignment mark 4 is provided in an optional position of the scribe area. When exposure surfaces D, E, H and I are exposed on a wafer 1, after a step and repeat stage 9 is step-delivered, a circuit pattern of a mask 11 is exposed by an X ray 13. When exposure surface C or G is exposed, after the stage 9 is moved only by an arrangement pitch of the chip 6, the alignment mark 4 of the mask 11 and on the wafer 1 are detected by an optical system 15, the chip 6 already exposed or the scribe area 7 are agreed with each other and registered, and the shutter 17 is moved to the registered portion, the X ray 13 is generated from the X ray source 12 and exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an improvement in Xa exposure that performs schedule-and-repeat. Regarding equipment.

[Background of the invention]

In the manufacturing process of semiconductors such as LSIs, circuit patterns are exposed on wafers.

When exposing this circuit pattern, effective use of the wafer (
It is necessary to expose the circuit pattern on the entire surface of the wafer without any gaps and to eliminate unnecessary parts of the wafer (hereinafter referred to as the effective utilization rate of the wafer).

On the other hand, in order to avoid overlapping exposure and wafer Ic
In order to facilitate the post-process of separating a large number of exposed circuits one by one into products, C must be arranged in an orderly manner for each circuit (hereinafter referred to as throughput).

For this purpose, it is a good idea to include as many circuit patterns as possible on the -th exposure surface, and to do this, the light path area inevitably increases.

The effective utilization rate and throughput of the wafer described above are in a mutually contradictory relationship. This will be explained in more detail.

For example, the one shown in Figure 2 is a 5-inch sea urchin... 2 in 1
When exposure is performed step-and-repeat using exposure surface 2 having an exposure area of 0m square, 2
Four shot exposure can be performed, and almost the entire surface of the wafer 1 can be used effectively. However, in this case 2
In the 0-simplified square exposure (2), there are eight chips 6 on which circuit patterns are formed, and therefore, the number of chips exposed on the wafer 1 by one shot exposure is eight.

On the other hand, in the example shown in Figure 3, the exposure area is set to 30 dark squares. In this case, only 9 shots can be exposed, and there is a lot of wasted area on the sea urchin...1 that is not exposed. , the effective utilization of wafers is greatly reduced. The number of chips 6 exposed by one shot is 18, and the throughput is greatly improved.

As a compromise plan that satisfies both of these requirements, if the arrangement is as shown in Figure 4, the following problems arise.

In this case, 12 shots of 50wn square exposure surface 3 are distributed on 5-inch wafer 1! This is what I did. Also chip 6
The number of is 18.

In this arrangement, alignment between the mask and the wafer 1 in each exposure is performed by the alignment mark 4 provided in the scribe area 7 of the chip 6 (see FIG. 5), as can be seen from the arrangement of the objective lens 5. However,
Of the exposure surface 3, C and F are located at the outer periphery of the wafer 1.

The G, J, and L alignment marks 4 protrude from the surface of the wafer 1 and cannot be aligned.

Therefore, when exposing the outer periphery of the wafer 1, the alignment mark 4 in the plane of the wafer 1 is first aligned, and then the stage is moved by a certain amount depending on the precision of the stage feed for alignment and exposure. was.

As a result, the exposure accuracy depends on the stage feed accuracy, resulting in double exposure, which reduces the yield of the outer periphery of wafer 1, and ultimately reduces the effective utilization rate of the wafer. .

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned conventional problems and provide a method and apparatus for exposing a wafer that simultaneously satisfies throughput and effective utilization of the wafer.

[Summary of the invention]

In other words, the present invention makes it possible to align the exposed area on the wafer and make effective use of the outer periphery of the wafer with a large exposure surface. The chips or scribe area K are positioned so as to partially overlap the pattern to be exposed, and the overlapping chips or scribe area are covered with a shutter, etc., and the entire surface of the wafer is exposed while preventing double exposure. The feature is that the circuit pattern is exposed.

The apparatus for carrying out this exposure is equipped with a step-and-repeat stage for loading the wafer and feeding the wafer in steps, and adjusting the relative position of the wafer and mask or the chip or scribe area on the adjacent exposure surface. An alignment optical system is installed to align the
The present invention is characterized by the provision of a movable mirror and a Xi source for covering the overlapping portion with the adjacent exposure surface to prevent double exposure.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below. 1st
The example shown in the figure shows a case where there are 18 chips 6 within the exposure surface 3. The chip 6 placed within this exposure surface 3 is the fifth chip.
As shown in the enlarged figure, a certain scribe area 7 is provided and arranged in an orderly manner.
An alignment mark 4 is provided at an arbitrary location. Therefore, the exposure surface 3 can be freely set for each arrangement pitch of the chips 6.

First, in the following explanation, it is assumed that the arrangement of the chips 6 within the exposure surface 3 is shown as shown in FIG.

That is, in the figure, the chips 6 are arranged in six rows from 6-1 to 6-6.
It is represented as 16 chips 6 arranged in three stages of A, B, and C.

In FIG. 4 (shaded areas indicate overlapping areas), first, the exposed surface 3 is placed in the center of the wafer 1.

D, g, 1(, I) are exposed.Next, VCC and G are already exposed in the 6-6 row and the three rows A11B and C of the chip 6. Columns A, B and B are overlapped on top of each other for alignment, and the shutters are placed over the overlapped portions to expose exposure surfaces C and G.

Therefore, in this case, the exposure surface C exposed on the wafer 1,
Chip 6#'i of a, i in rows 6-1 to 6-5.

There are only three steps: mouth and ha.

In this case, depending on the size of the wafer 1, it is possible to stack two rows of chips 6 or to stack them one on top of the other.

The exposure surfaces F and J are exposed by overlapping the rows of chips 6-1 on the exposure surfaces F and j with the rows of chips 6-6 on the exposed surfaces E and I that have already been exposed, and then exposure ΣF.

J is aligned and exposed in the same manner.

Next, for exposure surfaces A and BK, the C stage of the chips 6 of the exposed surfaces A and B and the A stage of the exposure WD and E that have already been exposed are overlapped and positioned, and then this overlapped part is covered with a shutter and exposed. In this case, the chips 6 exposed on the wafer 1 are in rows 6-1 to 6-6 of A and ;.

Of course, in this case as well, depending on the size of the wafer 1, the number of stacked layers can be freely determined.

Similarly, for the exposed surfaces K and L, the A step of the exposure 'fK and L and the C step of the exposed surface H and the exposure surface L, which have already been exposed, are superimposed.

In this way, the chips 6 already exposed on the surface of the wafer 1
Alternatively, by aligning the chip 6 or the scribe area 7 of the exposure surface 3 to be exposed to the scribe area 7, accurate alignment can be performed, and the size K of the exposure surface 5 is irrelevant, and the wafer 1 The maximum amount of effective VCn light is applied to the outer circumference of the area.

Next, the device will be explained. In FIG. 7, 9 is a step-and-repeat stage 6D, which moves stepwise on the base 8 with the wafer 1 mounted thereon. 10
is a wafer chuck. Reference numeral 15 denotes an alignment optical system for detecting the alignment mark 4 on the exposure surface of the wafer (see FIG. 5) and the alignment mark on the mask 11. 17 is a movable shutter; drive unit 16;
moved by 12 is an xa source, 13 is an X-ray, 14
is a helium champer.

In this apparatus, when performing the exposure shown in FIG. 4, it is performed as follows.

First, when exposing the exposure side E, H, and I on the wafer 1, the step-and-repeat stage 9 is moved step by step, and the circuit pattern of the mask 110 is exposed to the X-rays 13 generated from the X-ray source 12. do. Next, when exposing the exposure surface 〇 or G, the step-and-repeat stage 9 is moved by the arrangement pitch of the chips 6, and the alignment mark 4 exposed on the wafer 1 and the alignment mark 4 of the mask 11 are aligned. The alignment optical system 15 detects the area, aligns and overlaps the already exposed chip 6 or scribe area 7, moves the 7-pointer 17 to that area, and then moves the X-ray source 12 to the pxs 13. The same process is performed for the exposure surfaces A, B, F, J, K and L, which are generated and exposed.

〔Effect of the invention〕

As described in detail above, according to the exposure method of the present invention, the pattern of the mask to be exposed is superimposed and positioned on nine parts of the wafer surface that have already been exposed, and the overlapping part is covered with a shutter. As a result, alignment can be performed accurately, and the outer peripheral portion of the wafer can be utilized to the maximum regardless of the size of the exposure surface, and throughput and wafer usage efficiency can be improved at the same time.

In addition, a step-and-repeat stage for step-feeding the wafer and an alignment optical system for aligning the wafer and mask were installed, and a movable shutter covered the overlapping areas for exposure. Double exposure was prevented, and throughput and wafer usage efficiency in exposing wafers could be improved at the same time.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an aspect of the exposure method of the present invention. 2 to 4 are plan views showing aspects of the conventional exposure method. FIG. 4 shows a case in which the throughput is improved by increasing the area, and a case in which the effective rate of use is increased while keeping the exposed area large. FIG. 5 is an explanatory diagram showing a partially enlarged plan view of the chip arrangement portion, and FIG. 6 is an explanatory diagram showing a plan view showing the arrangement of chips on the exposure surface. FIG. 7 is a cross-sectional view showing one embodiment of an apparatus for carrying out the method of the invention. 1... Wafer, 3... Exposure surface, 4... Alignment mark, 6... Chip, 7... Scribe area. 9...Step and repeat stage. 11...Mask, 12...X-ray source. 15... Alignment optical system. 16...Shutter drive unit. 17...Movable shutter. / Figure 2 Figure 3 Figure 4 Figure

Claims (2)

[Claims] (1) In step-and-repeat exposure, in which the entire wafer is exposed to light by repeating the step-feeding of the wafer several times, and exposing the entire surface of the wafer to light, the exposed surface is made by aligning multiple chips with circuit patterns with a certain scribe area. The wafer is placed over the chip or scribe area on the exposed surface of the wafer, and the overlapping chip is covered with a shutter, etc. to prevent double exposure and expose the circuit pattern to the entire surface of the wafer. Exposure method. (2) A step-and-repeat stage for mounting a wafer and feeding the wafer in steps, and an alignment for relative positioning of the wafer and mask, or alignment with a chip or scribe area on an adjacent exposure surface. a movable shutter for covering the overlapping portion between the optical system and the adjacent exposure surface to prevent double exposure;
A wafer exposure device consisting of a line source.