JPS6196098A - Gold plated electronic parts - Google Patents

Gold plated electronic parts

Info

Publication number
JPS6196098A
JPS6196098A JP21613284A JP21613284A JPS6196098A JP S6196098 A JPS6196098 A JP S6196098A JP 21613284 A JP21613284 A JP 21613284A JP 21613284 A JP21613284 A JP 21613284A JP S6196098 A JPS6196098 A JP S6196098A
Authority
JP
Japan
Prior art keywords
plating
films
electronic parts
pads
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21613284A
Other languages
Japanese (ja)
Inventor
Toshihiko Oota
敏彦 太田
Masao Sekihashi
関端 正雄
Osamu Miyazawa
修 宮沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21613284A priority Critical patent/JPS6196098A/en
Publication of JPS6196098A publication Critical patent/JPS6196098A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE:To manufacture Au plated electronic parts preventing the stripping of the plating and having high reliability by successively plating electronic parts with Ni and Co before plating with Au. CONSTITUTION:A dibonding pad 2a, a wire bonding pad 2b and pads 2c each provided with a lead are formed on a multilayer wiring ceramic board 1 for mounting a semiconductor. Ni films 3 are formed on the pads 2a, 2b, 2c by electroless plating or electroplating, and leads 5 are connected to the pads 2c with eutectic Ag brazing filler metal 4. Ni films 6 of 2-5mum thickness are further formed by electroplating. The Ni films 6 are plated with Co 7 to 0.5mum thickness, and Au films 8 of 2mum thickness are formed on the Co films 7 by plating. A semiconductor pellet 9 is then dibonded with wires 10, a sealing cap 11 is airtightly put on the board 1 and the leads 5 are dipped in molten solder.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、金属面上に金メッキを有する電子部品に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electronic component having gold plating on a metal surface.

〔発明の背景〕[Background of the invention]

電子部品に於て、金はダイボンディング性。 In electronic parts, gold has die bonding properties.

ワイヤーボンディング性、ハンダ付性、耐熱色耐食性等
が秀れていることより、各種の電子部品に金メッキを施
し、広く利用されている。
Due to its excellent wire bondability, solderability, heat resistance, color corrosion resistance, etc., it is widely used for gold plating on various electronic components.

セラミックにメタライズを施した電子部品の製造法とし
ては、メタライズ層上に無電解ニッケルメッキもしくは
電気ニッケルメッキ皮膜を形成し、その後共晶Agロー
でリード付を行なつだ後、電気ニッケル、電気金メッキ
を行なうが、半導体パッケージング時の加熱条件(例え
ば450°C110分程度)は過酷である。特にダイボ
ンディング、ワイヤーボンディング後のガラス封止加熱
により、ダイポンディングしたペレット中のシリコンが
金メッキの下地メッキとして施したニッケル中に拡散し
、ニッケルーシリコンの合金層が形成され、シリコンが
拡散したニッケルーシリコン合金層とシリコンが拡散し
てないニッケル層の界面よりメッキ剥れが生じるという
不良が発生し、信頼性上大きな問題となる。本対策の為
に金メッキの下地メッキとして施した電気ニッケルメッ
キ後加熱処理(リード付を行なうためのAgロウの融点
よりも若干低い温度)を施す方法があるが、加熱条件を
シビアに管理する必要があると同時に、電気ニッケルメ
ッキ後加熱処理を行なうことより、連続的に金メッキが
出来ず、工程数が増し、生産性が低下する。
The manufacturing method for electronic components using metallized ceramic is to form electroless nickel plating or electrolytic nickel plating film on the metallized layer, then attach leads with eutectic Ag row, and then electrolytic nickel or electrolytic gold plating. However, the heating conditions (for example, 450° C. for about 110 minutes) during semiconductor packaging are harsh. In particular, by heating the glass seal after die bonding and wire bonding, the silicon in the die bonded pellets diffuses into the nickel applied as the base plating for gold plating, forming a nickel-silicon alloy layer, and forming a nickel-silicon alloy layer. A defect occurs in which plating peels off from the interface between the silicon alloy layer and the nickel layer where silicon has not diffused, which poses a major problem in terms of reliability. To counter this, there is a method of applying heat treatment (at a temperature slightly lower than the melting point of Ag solder for attaching leads) after electrolytic nickel plating, which is applied as a base plating for gold plating, but the heating conditions must be strictly controlled. At the same time, since heat treatment is performed after electrolytic nickel plating, gold plating cannot be performed continuously, the number of steps increases, and productivity decreases.

なお、金メッキの薄層化を目的として、金の下地メッキ
としてN 1−Co合金メッキ(特開昭55−5469
2 ) 、あるいはRhメッキ(%開昭58−4955
 )の検討が行なわれている。
In addition, for the purpose of thinning the gold plating layer, N1-Co alloy plating (Japanese Patent Laid-Open No. 55-5469
2) or Rh plating (% 1986-4955)
) are being considered.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、メッキ剥れのない高信頼性の電子部品
を提供することにある。
An object of the present invention is to provide a highly reliable electronic component without peeling of plating.

〔発明の概要〕[Summary of the invention]

金メッキの下地として電気ニッケルメッキし、その上に
コバルトメッキを行なうことにより、コバルトが半導体
パッケージング時の過酷な加熱においてペレット中のシ
リコンがニッケルに拡散することを防止するバリアーと
して有効に働くことを見い出したものである。コバルト
がシリコンの拡散を防止することKより、電気ニッケル
後の加熱処理を施すことなくメッキ剥れ不良現象が皆無
となり、高信頼性でしかも電気ニッケル、コバルト、金
メッキと連続的に行なうことが出来る。
By electrolytically plating nickel as a base for gold plating and then plating cobalt on top of it, we have found that cobalt acts effectively as a barrier to prevent the silicon in the pellet from diffusing into nickel during the severe heating during semiconductor packaging. This is what I discovered. Because cobalt prevents the diffusion of silicon, there is no plating failure phenomenon without heat treatment after electrolytic nickel, and it is highly reliable and can be performed continuously with electrolytic nickel, cobalt, and gold plating. .

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を矛1図により説明する。 Embodiments of the present invention will be described below with reference to FIG.

半導体を搭載する多層配線セラミック基板1はダイポン
ディングパッド2ae ワイヤーポンディングパッド2
b、 リード付パッド2Cを有し、これらのパッドはW
もしくは鳩等の高融点金属ペーストを使用する。これは
セラミックの焼結前にスクリーン印刷法などで形成して
おき、セラミック基板1を焼結する時、セラミックとこ
れら金属が相互に焼結し、セラミックと一体となったメ
タライズパッド2a〜2Cが形成される。その後このパ
ッド上にニッケルメッキ皮膜3を無電解もしくは電気忙
て形成する。その後リード接続を必要とするパッド2C
に例えば共晶銀ロウ材4でロウ付法によりリード5を接
続する。引き続き、電気メツキ法においてニッケルメッ
キ皮膜6を2〜5μm形成する(例えばワット浴、スル
ファミン酸浴)。そしてこのニッケルメッキ皮膜6上に
α5μmのコバルトメッキ7(硫酸コバル) 4sog
/j、  [化:l ハル) 45g/l、  ホウ酸
40 g/ lの組成液)を施し、さらKその上に金メ
ツキ皮膜8 (EEJA製純金メッキ液で例工ばテンペ
レックス401 )を2岬形成する。金メツキ後、半導
体ペレット9をダイポンディングし、ワイヤー10にて
ポンディング後、封止キャップ11(例えばセラミック
製でガラス印刷したもの)にて気密封止し、その後リー
ド5Vc半田デイツプを行なう。
A multilayer wiring ceramic substrate 1 on which a semiconductor is mounted has a die bonding pad 2ae and a wire bonding pad 2.
b. It has pads 2C with leads, and these pads are W
Or use a high melting point metal paste such as pigeon. This is formed by a screen printing method or the like before sintering the ceramic, and when the ceramic substrate 1 is sintered, the ceramic and these metals are mutually sintered, and the metallized pads 2a to 2C integrated with the ceramic are formed. It is formed. Thereafter, a nickel plating film 3 is formed electrolessly or electrically on this pad. Pad 2C which then requires a lead connection
For example, the leads 5 are connected by a brazing method using a eutectic silver brazing material 4. Subsequently, a nickel plating film 6 with a thickness of 2 to 5 μm is formed by electroplating (eg, Watt bath, sulfamic acid bath). Then, on this nickel plating film 6, α5 μm cobalt plating 7 (cobal sulfate) 4sog
/j, [Chemical: l Hull] 45g/l, boric acid 40g/l), and then gold plating film 8 (for example, Temperex 401 using pure gold plating liquid made by EEJA) was applied on top of it. Two capes are formed. After gold plating, the semiconductor pellet 9 is die-bonded, and after bonding with a wire 10, it is hermetically sealed with a sealing cap 11 (for example, made of ceramic and printed with glass), and then the lead 5Vc solder dip is performed.

金メッキ後種々の評価試験を行なった。ポンディングは
430°Cで窒素雰囲気中においてペレットをスクラブ
しながら行ない、X線透視で金/シリコン共晶で90%
以上濡れているものを良好とした。その後ダイボンドし
たサンプルをエアー中で460°0.15分加熱した後
、温度サイクルテスト(例えば+1509C,−55°
C,500−。
After gold plating, various evaluation tests were conducted. Bonding was carried out at 430°C in a nitrogen atmosphere while scrubbing the pellets, and the gold/silicon eutectic was 90% fluoroscopically determined.
Items that were wetter than above were considered good. After that, the die-bonded sample was heated in air at 460°C for 0.15 minutes, and then subjected to a temperature cycle test (e.g. +1509C, -55°C).
C,500-.

1.000サイクル)を行ない、ペレットの下のメッキ
剥れかないものを良品とした。いずれの場合も全(異常
は認められず充分良好な結果を得た。なお、ワイヤーポ
/ディング性、およびリードの半田付性も良好な結果を
得た。
1,000 cycles), and those with no peeling of the plating under the pellets were considered good. In all cases, sufficiently good results were obtained with no abnormalities observed. Also, good results were obtained in terms of wire podding and lead soldering.

ナ%  j−L  :! n !  m ml  (+
 t+  II  −L’  E  −1,#+ レト
 M’−i:  #ケージの例を示したが、リードレス
のパッケージにおいても同様に適用できる。
Na% j-L :! n! m ml (+
t+II-L'E-1, #+LetoM'-i: #Although an example of a cage is shown, it can be similarly applied to a leadless package.

〔発明の効果〕〔Effect of the invention〕

本発明忙よれば、メッキはがれのない高信頼性の金メツ
キ電子部品が得られる。
According to the present invention, a highly reliable gold-plated electronic component without peeling of the plating can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図である。 1・・・多層セラミック基板、2a・・・ダイポンディ
ングパッド、2b・・・ワイヤーポンディングパッド、
2C・・・リード付ハツト、3・・・ニッケルメッキ皮
膜、4・・・共晶Agロウ材、5・・・リード、6・・
・電気ニッケルメッキ皮膜、7・・・電気コバルトメッ
キ皮膜、8・・・電気金メッキ皮膜、9・・・半導体ペ
レット、10・・・ワイヤー、11・・・封止キャップ
FIG. 1 is a sectional view showing one embodiment of the present invention. 1... Multilayer ceramic substrate, 2a... Die bonding pad, 2b... Wire bonding pad,
2C... Hat with lead, 3... Nickel plating film, 4... Eutectic Ag brazing material, 5... Lead, 6...
- Electrolytic nickel plating film, 7... Electrolytic cobalt plating film, 8... Electrolytic gold plating film, 9... Semiconductor pellet, 10... Wire, 11... Sealing cap.

Claims (1)

【特許請求の範囲】[Claims] 金属面上に金メッキを施す電子部品に於て、ニッケルメ
ッキ上にコバルトメッキをし、該コバルトメッキ上に金
メッキを施すことを特徴とする金メッキされた電子部品
A gold-plated electronic component in which gold plating is applied to a metal surface, and the electronic component is characterized in that cobalt plating is applied on the nickel plating, and gold plating is applied on the cobalt plating.
JP21613284A 1984-10-17 1984-10-17 Gold plated electronic parts Pending JPS6196098A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21613284A JPS6196098A (en) 1984-10-17 1984-10-17 Gold plated electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21613284A JPS6196098A (en) 1984-10-17 1984-10-17 Gold plated electronic parts

Publications (1)

Publication Number Publication Date
JPS6196098A true JPS6196098A (en) 1986-05-14

Family

ID=16683761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21613284A Pending JPS6196098A (en) 1984-10-17 1984-10-17 Gold plated electronic parts

Country Status (1)

Country Link
JP (1) JPS6196098A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6488367B1 (en) 2000-03-14 2002-12-03 Eastman Kodak Company Electroformed metal diaphragm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6488367B1 (en) 2000-03-14 2002-12-03 Eastman Kodak Company Electroformed metal diaphragm

Similar Documents

Publication Publication Date Title
KR100318818B1 (en) Protective film bonding to leadframe
US4675243A (en) Ceramic package for semiconductor devices
JP3760075B2 (en) Lead frame for semiconductor packages
JPS6013078B2 (en) Gold-plated electronic components and their manufacturing method
US6519845B1 (en) Wire bonding to dual metal covered pad surfaces
JPS6243343B2 (en)
JP3475558B2 (en) Ball for bonding semiconductor chip and method for bonding semiconductor chip
JPH01257356A (en) Lead frame for semiconductor
JPS6196098A (en) Gold plated electronic parts
KR900003472B1 (en) Plating process for an electronic part
JPS5933851A (en) Airtightly sealed semiconductor container
JPS5838505B2 (en) Kouyūtenkinzokukushuhenometsukihou
JPS628532A (en) Gold-plated electronic component package
JPS62131526A (en) Gold plated electronic part
JPH1177371A (en) Soldering material, printed circuit board, and its manufacture
JPS628533A (en) Gold-plated electronic component package
JPS63137574A (en) Surface covering structure for metallized metal layer
JPS639957A (en) Semiconductor lead frame
JPS59149042A (en) Lead frame for semiconductor
JPH10284666A (en) Electronic component device
JPH08274242A (en) Semiconductor device and its manufacture
JP2743567B2 (en) Resin-sealed integrated circuit
JPH02174253A (en) Electronic parts package with rhenium layer at metal part
JPH03206633A (en) Semiconductor device
JPH0558259B2 (en)