JPS6195517A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6195517A JPS6195517A JP21715884A JP21715884A JPS6195517A JP S6195517 A JPS6195517 A JP S6195517A JP 21715884 A JP21715884 A JP 21715884A JP 21715884 A JP21715884 A JP 21715884A JP S6195517 A JPS6195517 A JP S6195517A
- Authority
- JP
- Japan
- Prior art keywords
- film
- diffusion layer
- sputtering
- oxide film
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 238000004544 sputter deposition Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000000992 sputter etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052786 argon Inorganic materials 0.000 abstract description 5
- 239000007789 gas Substances 0.000 abstract description 5
- 230000006378 damage Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 238000004140 cleaning Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 15
- 229910052719 titanium Inorganic materials 0.000 description 15
- -1 argon ions Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係り、特Ｋ、半導体
基板上に形成された半導体領域と配線層との間く形成さ
れる微細面積のコンタクトの信頼性を高める方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and particularly for manufacturing a microscopic area formed between a semiconductor region formed on a semiconductor substrate and a wiring layer. Concerning how to increase the credibility of your contacts.
半導体装置の分野では、１９７０年代以降、特に、高集
積化への傾向は強まる一方となり、超大規模集積回路（
超ＬＳＩ）へと進歩し、１つの半導体チップ上にコンピ
ュータ等のシステムが構成されるまでになってきている
。In the field of semiconductor devices, since the 1970s, the trend towards higher integration has been particularly strong, and ultra-large scale integrated circuits (
The technology has advanced to the point where systems such as computers can now be constructed on a single semiconductor chip.
ところで集積回路の高速化と高集積化は素子の微細化に
よって実現される。例えばＭＯ８集積回路では、素子の
微細化に伴い、多結晶シリコンゲート電極や、ソース拡
散層、ドレイン拡散層等と金属配線層との間で電気的接
続を行うためのコンタクト部の面積は縮／Ｊ＼されると
共にＰＮ接合の深さＫついても浅くなるように形成され
ることが必要となってくる。Incidentally, higher speed and higher integration of integrated circuits are achieved by miniaturization of elements. For example, in MO8 integrated circuits, as devices become smaller, the area of contact areas for making electrical connections between polycrystalline silicon gate electrodes, source diffusion layers, drain diffusion layers, etc. and metal wiring layers shrinks. Along with this, it becomes necessary to form the PN junction so that its depth K becomes shallow.
しかしながら、コンタクト面積の縮小化あるいはＰＮ接
合が浅く形成されるのに伴い、コンタクト抵抗の増加や
電極形成によるＰＮ接合の破壊等の問題が顕在化してく
る。特に超ＬＳＩの場合、数ミリ角のシリコンチク１１
個当たり、百方側以上のコンタクトが存在するため、こ
のような接続特性の劣化は素子の信頼性の低下につなが
り、集積回路の高速化、高集積化への大きな障害となっ
ている。However, as the contact area is reduced or the PN junction is formed shallower, problems such as increased contact resistance and destruction of the PN junction due to electrode formation become apparent. Especially in the case of ultra-LSI, silicon chips of several millimeters square 11
Since there are contacts on more than 100 sides per device, such deterioration in connection characteristics leads to a decrease in reliability of the device, and is a major obstacle to increasing the speed and integration of integrated circuits.
例えば、第２図に示す如く、Ｐ型のシリコン基板１１内
に砒素（Ａ、）イオンをイオン注入して形成されたＮ＋
型シリコン拡散層１２に対し、 絶縁膜としての酸化シ
リコン膜１３内に穿孔されたコンタクト窓１４を介して
アルミニウム（Ａｔ）電極巧を形成した場合、シリコン
基板上に存在する自然酸化膜１６のためにしばしば接触
抵抗が高くなったり接続不良が生じたりする等の問題が
生じていた。For example, as shown in FIG. 2, an N+
When an aluminum (At) electrode layer is formed on the type silicon diffusion layer 12 through the contact window 14 drilled in the silicon oxide film 13 as an insulating film, due to the natural oxide film 16 existing on the silicon substrate. However, problems such as high contact resistance and poor connections often occur.
そこでこのような問題を解決する技術として、前記シリ
コン基板１１上の自然酸化膜１６を不活性ガス中でスパ
ッタリングによりエツチング除去し、シリコン基板の清
浄な表面を露出させた後、真空を破らないでそのまま連
続的にアルミニウム電極を形成する方法が注目されてい
る。Therefore, as a technique to solve this problem, the natural oxide film 16 on the silicon substrate 11 is etched away by sputtering in an inert gas to expose the clean surface of the silicon substrate, and then the vacuum is not broken. A method of continuously forming aluminum electrodes is attracting attention.
この方法は、第３図に示す如く、コンタクト窓１４の底
部の拡散層１２上の自然酸化膜１６を１例えば＋
アルゴン（Ａｒ）等の不活性ガス中でスパッタリングに
より除去するものであるが、このスパッタリング時に、
コンタクト窓の外側の酸化シリコン膜も同時にスパッタ
リングされ、これらが又、コンタクト窓の底部に堆積し
、拡散層１２の表面が汚染され、清浄な表面が得られな
い等の問題を残していた。又、アルゴンイオンが、露呈
した拡散層表面をスパッタリングし、拡散層１２が損傷
を受け、特に、浅いＰ−Ｎ接合の場合にはリーク電流が
増加するという不都合があった。In this method, as shown in FIG. 3, the native oxide film 16 on the diffusion layer 12 at the bottom of the contact window 14 is removed by sputtering in an inert gas such as argon (Ar). During this sputtering,
The silicon oxide film on the outside of the contact window is also sputtered at the same time, and these also deposit on the bottom of the contact window, contaminating the surface of the diffusion layer 12 and leaving a problem that a clean surface cannot be obtained. In addition, argon ions sputter the exposed surface of the diffusion layer, damaging the diffusion layer 12 and increasing leakage current, especially in the case of a shallow PN junction.
このように、スパッタリング法によるコンタクト表面の
清浄化には上述の如き問題点を残しており、実用デバイ
スへの適用は困難であった。As described above, cleaning the contact surface by the sputtering method still has the above-mentioned problems, making it difficult to apply it to practical devices.
本発明は、前記実情に鑑みてなされたもので、微細でか
つ浅い接合をもつ半導体層に対しても接合特性を劣化さ
せることなく、オーミックコンタクトの良好な配線層を
形成し、信頼性の高い半導体装置を提供することを目的
とする。The present invention has been made in view of the above-mentioned circumstances, and is capable of forming a wiring layer with good ohmic contact without deteriorating the bonding characteristics even for a semiconductor layer having a fine and shallow junction, thereby achieving high reliability. The purpose is to provide semiconductor devices.
そこで、本発明では、絶縁膜に対して、コンタクト窓を
形成した後、該コンタクト窓の底部および絶縁膜上に薄
い金属層を形成しておき、この金属層の上から不活性ガ
スによるスパッタリング清浄化を行ない、その後に配線
金属層を形成するようにしている。Therefore, in the present invention, after forming a contact window on an insulating film, a thin metal layer is formed on the bottom of the contact window and on the insulating film, and sputtering cleaning with an inert gas is performed from above the metal layer. After that, a wiring metal layer is formed.
本発明によれば浅いＰＮ接合をもつ拡散層への微細なコ
ンタクトを形成するに際して、コンタクト窓の底部およ
び絶縁膜上に形成された薄い金属層の上からスパッタエ
ツチングを行なうようにしているため、絶縁膜自体のス
パッタリングによるコンタクト底部の汚染を防止すると
共に、拡散層表面の損傷を防止し得、低抵抗であってか
つ信頼性の高いオーミックコンタクトを得ることが可能
となる。According to the present invention, when forming a fine contact to a diffusion layer having a shallow PN junction, sputter etching is performed from the bottom of the contact window and the thin metal layer formed on the insulating film. It is possible to prevent contamination of the bottom of the contact due to sputtering of the insulating film itself, and also to prevent damage to the surface of the diffusion layer, making it possible to obtain an ohmic contact with low resistance and high reliability.
以下、本発明の実施例について図面を参照しつつ詳細に
説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａｌ〜（ｄ）は、本発明Ｃ十実施例であるオー
ミックコンタクトの形成工程を示すものである。FIGS. 1A to 1D show the process of forming an ohmic contact according to the C10 embodiment of the present invention.
まず、第１図（ａ）に示す如（、Ｐ型のシリコン基板１
内に砒素イオンをイオン注入してＮ＋型シリコン拡散層
２を形成した後、絶縁膜として酸化シリコン膜３を堆積
し、この酸化シリコン膜３に対しコンタクト窓４を穿孔
する。この時、コンタクト窓４底部の該拡散層２上には
、自然酸化膜５（酸化シリコン膜）が生成されている。First, as shown in FIG. 1(a), a P-type silicon substrate 1
After forming an N+ type silicon diffusion layer 2 by implanting arsenic ions inside the structure, a silicon oxide film 3 is deposited as an insulating film, and a contact window 4 is formed in the silicon oxide film 3. At this time, a natural oxide film 5 (silicon oxide film) is formed on the diffusion layer 2 at the bottom of the contact window 4.
次いで、第１図（ｂ）に示す如く、膜厚約数子〜数百Ａ
のチタン膜６を蒸着法によって形成する。Next, as shown in FIG.
A titanium film 6 is formed by a vapor deposition method.
続いて、第１図（Ｃ）に示す如く、アルゴンガスを用い
たスパッタリングによって、基板１表面をエツチングす
る。このとき、エツチングの深さは、該チタン膜６と自
然酸化膜５を全てエツチングする程度で良い。この工程
では、コンタクト窓底部の拡散層２上の自然酸化膜５が
ほぼスパッタリングされて除去されると共に、スパッタ
リングによって気相中に放出されたチタンの１部がコン
タクト孔底部の拡散層上に再び析出することおよび該拡
散層表面に打ち込まれたりすることにより、拡散層２上
にチタン薄膜７が生成され低抵抗のオーミックコンタク
トが形成される。Subsequently, as shown in FIG. 1(C), the surface of the substrate 1 is etched by sputtering using argon gas. At this time, the etching depth may be such that the titanium film 6 and the natural oxide film 5 are all etched. In this step, the natural oxide film 5 on the diffusion layer 2 at the bottom of the contact window is almost completely removed by sputtering, and a part of the titanium released into the gas phase by sputtering is returned onto the diffusion layer at the bottom of the contact hole. By being deposited and implanted into the surface of the diffusion layer, a titanium thin film 7 is generated on the diffusion layer 2, forming a low resistance ohmic contact.
そして、この後、真空を破ることなく連続的に配線金Ｉ
Ｋ膜としてのアルミニウム薄膜８を真空蒸着法によって
第１図（ｄ）に示す如く形成する。After this, the wiring metal I is continuously applied without breaking the vacuum.
An aluminum thin film 8 as a K film is formed by vacuum evaporation as shown in FIG. 1(d).
このように、薄いチタン膜６を基板１表面全体に形成し
ておき、このチタン膜６の上から軽くスパッタリングを
行なうようにしているため、コンタクト孔の周りの酸化
シリコン膜のエツチングが表面のチタン膜の存在によっ
て抑制される。また、気相中ではチタンイオンの存在比
率が高くなると１ 共に、周囲の絶縁膜中でコ
ンタクト孔底部にのみ拡散層が露呈しているため、この
拡散層上に、より多くのチタンが再析出するものと考え
られる。In this way, the thin titanium film 6 is formed on the entire surface of the substrate 1, and sputtering is performed lightly from above the titanium film 6, so that the etching of the silicon oxide film around the contact hole is not caused by the etching of the titanium film on the surface. suppressed by the presence of membranes. In addition, as the abundance ratio of titanium ions increases in the gas phase1, as the diffusion layer is exposed only at the bottom of the contact hole in the surrounding insulating film, more titanium is redeposited on this diffusion layer. It is considered that
また、チタンの析出によりて、拡散層表面にはチタン薄
＠７が存在することＫより、拡散層表面のスパッタリン
グによる損傷は大幅に低減される。Further, since a titanium thin film @7 exists on the surface of the diffusion layer due to the precipitation of titanium, damage caused by sputtering on the surface of the diffusion layer is significantly reduced.
このようにして形成された拡散層と配線金属層との間の
接続は、微細なコンタクト領域におけるコンタクト抵抗
を減少することができると共に洩いＰＮ接合面をもつ半
導体装置においてもリーク電流の増大を防止することが
でき、信頼性の高い低抵抗のオーミックコンタクトを得
ることが可能となる。The connection between the diffusion layer and the wiring metal layer formed in this way can reduce the contact resistance in the fine contact region and also prevent the increase in leakage current in semiconductor devices with leaky PN junction surfaces. This makes it possible to obtain a highly reliable, low-resistance ohmic contact.
なお、実施例においては、スパッタリングに先立ち形成
しておく薄い金属膜としてチタンを用いたが、必ずしも
チタンに限定されることなくタングステン（Ｗ）、モリ
ブデン（ＭＯ）等半導体領域に悪影響を与えない金属で
あればよい。In the examples, titanium was used as the thin metal film formed prior to sputtering, but it is not necessarily limited to titanium, and metals such as tungsten (W) and molybdenum (MO) that do not have an adverse effect on the semiconductor region may also be used. That's fine.
また、実施例においては、アルゴンイオンを用いたスパ
ッタエツチングを用いたが、必ずしもこれに限定される
ものではない。Further, in the embodiment, sputter etching using argon ions was used, but the invention is not necessarily limited to this.
第１図（ａ）乃至（ｄ）は本発明実施例の半導体装置の
製造方法を示す工程説明図、第２図は従来例の方法によ
って形成された半導体装置を示す図、第３図は従来例の
改善例である自然酸化膜のスパッタエツチング工程を示
す図（従来例）である。
１・・・Ｐ型のシリコン基板、２−・Ｎ生型シリコン拡
散層、３・・・酸化シリコン膜、４・・・コンタクト窓
。
５・−・自然酸化膜、６・・・チタン膜、７・・・チタ
ン薄膜（再析出膜）、８・・・アルミニウム薄膜、１１
・・・Ｐ型のシリコン基板、１２・・・Ｎ生型シリコン
拡散層、１３・・・酸化シリコン膜、１４・・・コンタ
クト窓、１５・・・アルミニウム電極、１６・・・自然
酸化膜。
第１ 図（Ｇ）
第 １ 図（ｄ）1(a) to 1(d) are process explanatory diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing a semiconductor device formed by a conventional method, and FIG. 3 is a diagram showing a conventional method. FIG. 3 is a diagram (conventional example) showing a sputter etching process for a natural oxide film, which is an improved example of the example; DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2--N raw silicon diffusion layer, 3... silicon oxide film, 4... contact window. 5... Natural oxide film, 6... Titanium film, 7... Titanium thin film (re-deposited film), 8... Aluminum thin film, 11
P-type silicon substrate, 12 N-type silicon diffusion layer, 13 silicon oxide film, 14 contact window, 15 aluminum electrode, 16 natural oxide film. Figure 1 (G) Figure 1 (d)
Claims (1)
絶縁膜に対し、該拡散層へのコンタクト用の窓を形成す
る穿孔工程と、形成された窓内および前記絶縁膜上に薄
い金属膜を形成する薄膜形成工程と、該拡散層表面に存
在する自然酸化膜を除去すべく、不活性ガスによるスパ
ッタエッチングを行なうスパッタリング工程と、スパッ
タリング後、連続的に配線金属膜を形成する配線層形成
工程とを備えたことを特徴とする半導体装置の製造方法
。A drilling process for forming a window for contacting the diffusion layer in an insulating film formed on the surface of the semiconductor substrate in which the diffusion layer is formed, and a thin metal film inside the formed window and on the insulating film. a thin film formation process to form a thin film, a sputtering process to perform sputter etching using an inert gas to remove the native oxide film existing on the surface of the diffusion layer, and a wiring layer formation process to continuously form a wiring metal film after sputtering. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21715884A JPS6195517A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21715884A JPS6195517A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195517A true JPS6195517A (en) | 1986-05-14 |
Family
ID=16699759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21715884A Pending JPS6195517A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195517A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6514804B1 (en) | 1999-05-20 | 2003-02-04 | Nec Corporation | Thin-film transistor and fabrication method thereof |
| JP2021111755A (en) * | 2020-01-15 | 2021-08-02 | 株式会社アルバック | Formation method of metal wiring |
| JP2021111757A (en) * | 2020-01-15 | 2021-08-02 | 株式会社アルバック | Formation method of metal wiring |
-
1984
- 1984-10-16 JP JP21715884A patent/JPS6195517A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6514804B1 (en) | 1999-05-20 | 2003-02-04 | Nec Corporation | Thin-film transistor and fabrication method thereof |
| KR100404351B1 (en) * | 1999-05-20 | 2003-11-01 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Thin-film transistor and fabrication method thereof |
| JP2021111755A (en) * | 2020-01-15 | 2021-08-02 | 株式会社アルバック | Formation method of metal wiring |
| JP2021111757A (en) * | 2020-01-15 | 2021-08-02 | 株式会社アルバック | Formation method of metal wiring |
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