JPS6195517A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow a wiring layer having good ohmic contact to be obtained without deterioration in junction characteristics by forming a thin metal film on the bottom of a contact window and an insulating film and cleaning the layer by sputtering it in an active gas from the upper side of the metal film. CONSTITUTION:After an N<+> type silicon diffusion layer 2 is formed in a P type silicon substrate 1, a silicon oxide film 3 is built up and a contact window 4 is bored. Next, when a titan film 6 is formed by an evaporation method and the surface of the substrate 1 is etched by sputtering argon gas, a natural oxide film 5 on the diffusion layer 2 at the bottom of the contact window is substantially removed, and at the same time, one part of titan discharged in the vapor phase is again deposited on the diffusion layer 2 at the bottom of the contact hole to form a titan film 7 by its implantation onto the surface of the diffusion layer. After this, an aluminum film 8 as a wiring metal film is formed by a vacuum evaporation method. This causes etching of the silicon oxide film 3 around the contact hole to be suppressed by the presence of the titan film 7 and at the same time, damages due to sputtering on the surface of the diffusion layer 2 to be largely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and particularly for manufacturing a microscopic area formed between a semiconductor region formed on a semiconductor substrate and a wiring layer. Concerning how to increase the credibility of your contacts.

[Technical background of the invention and its problems]

In the field of semiconductor devices, since the 1970s, the trend towards higher integration has been particularly strong, and ultra-large scale integrated circuits (
The technology has advanced to the point where systems such as computers can now be constructed on a single semiconductor chip.

Incidentally, higher speed and higher integration of integrated circuits are achieved by miniaturization of elements. For example, in MO8 integrated circuits, as devices become smaller, the area of contact areas for making electrical connections between polycrystalline silicon gate electrodes, source diffusion layers, drain diffusion layers, etc. and metal wiring layers shrinks. Along with this, it becomes necessary to form the PN junction so that its depth K becomes shallow.

However, as the contact area is reduced or the PN junction is formed shallower, problems such as increased contact resistance and destruction of the PN junction due to electrode formation become apparent. Especially in the case of ultra-LSI, silicon chips of several millimeters square 11
Since there are contacts on more than 100 sides per device, such deterioration in connection characteristics leads to a decrease in reliability of the device, and is a major obstacle to increasing the speed and integration of integrated circuits.

For example, as shown in FIG. 2, an N+
When an aluminum (At) electrode layer is formed on the type silicon diffusion layer 12 through the contact window 14 drilled in the silicon oxide film 13 as an insulating film, due to the natural oxide film 16 existing on the silicon substrate. However, problems such as high contact resistance and poor connections often occur.

Therefore, as a technique to solve this problem, the natural oxide film 16 on the silicon substrate 11 is etched away by sputtering in an inert gas to expose the clean surface of the silicon substrate, and then the vacuum is not broken. A method of continuously forming aluminum electrodes is attracting attention.

In this method, as shown in FIG. 3, the native oxide film 16 on the diffusion layer 12 at the bottom of the contact window 14 is removed by sputtering in an inert gas such as argon (Ar). During this sputtering,
The silicon oxide film on the outside of the contact window is also sputtered at the same time, and these also deposit on the bottom of the contact window, contaminating the surface of the diffusion layer 12 and leaving a problem that a clean surface cannot be obtained. In addition, argon ions sputter the exposed surface of the diffusion layer, damaging the diffusion layer 12 and increasing leakage current, especially in the case of a shallow PN junction.

As described above, cleaning the contact surface by the sputtering method still has the above-mentioned problems, making it difficult to apply it to practical devices.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is capable of forming a wiring layer with good ohmic contact without deteriorating the bonding characteristics even for a semiconductor layer having a fine and shallow junction, thereby achieving high reliability. The purpose is to provide semiconductor devices.

[Summary of the invention]

Therefore, in the present invention, after forming a contact window on an insulating film, a thin metal layer is formed on the bottom of the contact window and on the insulating film, and sputtering cleaning with an inert gas is performed from above the metal layer. After that, a wiring metal layer is formed.

〔Effect of the invention〕

According to the present invention, when forming a fine contact to a diffusion layer having a shallow PN junction, sputter etching is performed from the bottom of the contact window and the thin metal layer formed on the insulating film. It is possible to prevent contamination of the bottom of the contact due to sputtering of the insulating film itself, and also to prevent damage to the surface of the diffusion layer, making it possible to obtain an ohmic contact with low resistance and high reliability.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1D show the process of forming an ohmic contact according to the C10 embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
After forming an N+ type silicon diffusion layer 2 by implanting arsenic ions inside the structure, a silicon oxide film 3 is deposited as an insulating film, and a contact window 4 is formed in the silicon oxide film 3. At this time, a natural oxide film 5 (silicon oxide film) is formed on the diffusion layer 2 at the bottom of the contact window 4.

Next, as shown in FIG.
A titanium film 6 is formed by a vapor deposition method.

Subsequently, as shown in FIG. 1(C), the surface of the substrate 1 is etched by sputtering using argon gas. At this time, the etching depth may be such that the titanium film 6 and the natural oxide film 5 are all etched. In this step, the natural oxide film 5 on the diffusion layer 2 at the bottom of the contact window is almost completely removed by sputtering, and a part of the titanium released into the gas phase by sputtering is returned onto the diffusion layer at the bottom of the contact hole. By being deposited and implanted into the surface of the diffusion layer, a titanium thin film 7 is generated on the diffusion layer 2, forming a low resistance ohmic contact.

After this, the wiring metal I is continuously applied without breaking the vacuum.
An aluminum thin film 8 as a K film is formed by vacuum evaporation as shown in FIG. 1(d).

In this way, the thin titanium film 6 is formed on the entire surface of the substrate 1, and sputtering is performed lightly from above the titanium film 6, so that the etching of the silicon oxide film around the contact hole is not caused by the etching of the titanium film on the surface. suppressed by the presence of membranes. In addition, as the abundance ratio of titanium ions increases in the gas phase1, as the diffusion layer is exposed only at the bottom of the contact hole in the surrounding insulating film, more titanium is redeposited on this diffusion layer. It is considered that

Further, since a titanium thin film @7 exists on the surface of the diffusion layer due to the precipitation of titanium, damage caused by sputtering on the surface of the diffusion layer is significantly reduced.

The connection between the diffusion layer and the wiring metal layer formed in this way can reduce the contact resistance in the fine contact region and also prevent the increase in leakage current in semiconductor devices with leaky PN junction surfaces. This makes it possible to obtain a highly reliable, low-resistance ohmic contact.

In the examples, titanium was used as the thin metal film formed prior to sputtering, but it is not necessarily limited to titanium, and metals such as tungsten (W) and molybdenum (MO) that do not have an adverse effect on the semiconductor region may also be used. That's fine.

Further, in the embodiment, sputter etching using argon ions was used, but the invention is not necessarily limited to this.

[Brief explanation of drawings]

1(a) to 1(d) are process explanatory diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing a semiconductor device formed by a conventional method, and FIG. 3 is a diagram showing a conventional method. FIG. 3 is a diagram (conventional example) showing a sputter etching process for a natural oxide film, which is an improved example of the example; DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2--N raw silicon diffusion layer, 3... silicon oxide film, 4... contact window. 5... Natural oxide film, 6... Titanium film, 7... Titanium thin film (re-deposited film), 8... Aluminum thin film, 11
P-type silicon substrate, 12 N-type silicon diffusion layer, 13 silicon oxide film, 14 contact window, 15 aluminum electrode, 16 natural oxide film. Figure 1 (G) Figure 1 (d)

Claims (1)

[Claims] A drilling process for forming a window for contacting the diffusion layer in an insulating film formed on the surface of the semiconductor substrate in which the diffusion layer is formed, and a thin metal film inside the formed window and on the insulating film. a thin film formation process to form a thin film, a sputtering process to perform sputter etching using an inert gas to remove the native oxide film existing on the surface of the diffusion layer, and a wiring layer formation process to continuously form a wiring metal film after sputtering. A method for manufacturing a semiconductor device, comprising the steps of: