JPS6195396A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to semiconductor integrated circuit technology and to technology effective when applied to the operation timing system of a signal latch circuit and an output buffer in a semiconductor integrated circuit. The present invention relates to a technique effective for use in a liquid crystal drive signal output circuit. B. Background Art] In an LSI such as a liquid crystal driver, a drive signal for driving a common electrode or segment electrode of a liquid crystal display device is formed and output based on data supplied from a microcomputer or the like. . FIG. 3 shows an example of a block arrangement of such a liquid crystal driver LSI, in which blocks are formed by a data control circuit DCL based on a control signal such as a write enable signal WE supplied from a microcomputer. In response to write signal φW, data latch circuit DLT outputs write data D, #D, #D, which is output on the bus at that time.
capture and retain. The write data D, m1)a
teeth. The data is converted into serial data in the parallel/serial conversion circuit PSG and then written into the display memory RAM. Then, the segment driver SD generates, for example, 64 signals (hereinafter referred to as segment outputs) for driving the segment electrodes of the liquid crystal display device based on the data read out from the display memory RAM.SEGo=SEGs
s is formed and output. Furthermore, each segment output is made into an AC waveform to prevent deterioration of the liquid crystal. Therefore, in the liquid crystal driver LSI, a large number of segment outputs SEG 3 are changed simultaneously at a frequency of, for example, several tens to several hundreds of Hz.This eliminates noise from the power supply voltage Vss. However, from the microcomputer side, the write enable signal WE and write data D, -D3 are supplied completely unrelated to the timing of the segment output 5EGo=SEGsa.As a result, as shown in FIG. As shown, segment output SEG
When the timing of the change in i coincides with the low level period of the data latch signal φW, noise in the power supply voltage Via induced by the change in the segment force 5EGL causes
The inventor of the present invention has clarified that there is a problem that erroneous data may be taken into the latch circuit DLT. Regarding the above-mentioned liquid crystal driver LSI, for example, see ``Hitachi MO3LSI Data Book: LCD Driver LSIJ'' published by Hitachi, Ltd. in March 1983.
It is explained in detail on pages 160 to 181 of jl. [Object of the Invention] An object of the invention is to provide a liquid crystal driver L having an output circuit that simultaneously outputs a large number of signals and a data latch circuit.
The purpose of this invention is to prevent erroneous data from being latched in a semiconductor integrated circuit such as an SI and to improve the reliability of the circuit. The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings. [Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows. That is, based on a reference signal for forming an output signal and a signal indicating latch timing, a control circuit is configured that does not change the former signal while the latter signal is valid, and the control circuit controls the signal. By supplying the signal to the output circuit to form an output signal, the output signal is not changed at the timing when data is latched, thereby preventing erroneous data latching due to power supply noise accompanying changes in the output signal. This aims to achieve the above purpose of preventing. [Embodiment 1] WI shows an embodiment in which the present invention is applied to a liquid crystal driver LSI. In this embodiment, an LCD that divides the original oscillation signal supplied from the oscillation circuits O5 and C (see FIG. 3) and generates a reference timing clock CL for driving the liquid crystal display device.
An output signal CL from the drive timing generation circuit LTG,
A control circuit C0NT is provided which forms signals for controlling the common driver CD and segment driver SD based on the write enable signal WE and the write signal φW output from the data control circuit DCL. The control circuit C0NT of No. 4 includes an inverter G1, an AND gate circuit Gx-Gs, and a NOR gate circuit G4. It is constituted by a type of flip-flop circuit consisting of Gs. AND gate circuit G2 that constitutes this control circuit C0NT
A write signal φW as shown in FIG. 2 (3) is input to one input terminal of the , and a reference timing clock as shown in FIG. 2 (1) outputted from the LCD drive timing generation circuit LTG is input to the other input terminal. A signal CL obtained by inverting CL with an inverter G1 is applied. The input terminal of the other AND gate circuit aS is connected to the AND gate circuit G8.
The write signal φW, which is the same as the input to the input signal φW, and the reference timing clocks ct and fJi are respectively applied. As a result, the write enable signal WE, which comes in at a completely asynchronous timing with the reference timing clock CL,
When the write signal φW formed based on is changed to low level, during the period of the low level, the control circuit C
The timing clock CL' output from 0NT is kept unchanged. That is, as shown in the second @, when the reference timing clock CL is at a low level, the write signal φW changes from a high level to a low level. The output timing clock CL' is at a low level while the write signal φW is at a low level. Stretched out so as not to change to a high level. Also, when the write signal φW changes from high level to low level while the reference timing clock CL is high level, the high level period of the timing clock CL' is set so that it does not change to high level while the write signal φW is low level. Stretched out. The timing clock CL' whose pulse width has been expanded or contracted as described above is provided at the entrance of the segment driver SD, and a display data signal regarding the segment electrodes read from the display memory RAM is applied to one input terminal. It is commonly applied to the other input terminal of the exclusive NOR circuit aoo"asa. As a result, the segment driver SD generates a timing clock as shown in FIG. 2 (2) according to one display data. C
AC waveform segment output S that changes in synchronization with L'
Form and output E Go = S E G sa. Similarly, the timing clock CL is supplied to the inverter INV provided at the entrance of the common driver CD, and the common driver CD is supplied with the timing clock CL.
' forms and outputs a common output COM with an AC waveform that changes in synchronization with '. In this way, in the liquid crystal driver/<LSI of the above embodiment, the outputs of the segment driver SD and the common driver CD as output circuits correspond to the write signal φW instructing the latch timing of the write data D, -D. The low level period is kept unchanged. Therefore, even if noise occurs in the voltage Vss at the timing shown as ZXm t2 in Figure 2 (5) due to a change in the output after the write signal φW rises, the noise has already been This is because the input data o and -D are fixed. There is no possibility that erroneous data will be taken into the latch circuit DLT. Note that in the above embodiment, the control circuit C0NT is connected to the inverter Q1. Although it is constituted by a flip-flop circuit consisting of AND gate circuits Gz, Gs and NOR gate circuit G4*Gg, it can be replaced with a logic gate circuit having a similar function. - Although the description has been given of the application to a static drive type (therefore, one common output) liquid crystal driver LSI, the present invention is not limited to this, and can be applied to an hour/minute ma drive type liquid crystal driver LSI having multiple common outputs. can do. Incidentally, to supplementally explain the liquid crystal driver LSI shown in No. 311, the LCD drive timing generation circuit LTG
is reset by a control signal 5YNC supplied from the outside to synchronize the internal clock. Further, the RAM write timing generation circuit RTG forms a write timing signal to the display memory RAM based on the original oscillation signal and the write signal φW supplied from the data control circuit OCT. The data latch circuit DLT takes in 8-bit display data and its address in 4-bit units in a time-division manner, and the previous 8-bit display data is supplied to the parallel/serial conversion circuit PSC and converted into serial data. . Furthermore, the 8-bit address taken into the data latch circuit DTL is supplied to the address decoder AD, and is stored in the display memory RAM where the serial display data output from the parallel/serial conversion circuit PSC is written. The corresponding address of is selected by address decoder AD. Furthermore, this liquid crystal driver LSI has a mode for turning off the liquid crystal based on an external control signal SB.
A mode setting latch circuit MIL is provided for switching between modes prepared in I.

【effect】

In a semiconductor integrated circuit such as a liquid crystal driver LSI that has an output circuit that simultaneously outputs a large number of signals and a data latch circuit, a signal that is a reference signal for forming an output signal and a signal that indicates latch timing is used. Therefore, a control circuit is provided that does not change the former signal while the latter signal is valid, and the output signal of this control circuit is supplied to an output circuit such as a segment driver or common driver, so that it can be used as a liquid crystal drive signal. Since the output signal is created so that the output signal does not change at the timing of data latching, erroneous data latching due to power supply noise accompanying changes in the output signal is prevented. This has the effect of improving the reliability of one circuit. Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and can be modified in various ways without departing from the spirit thereof. It goes without saying that L's [Field of Application] The above explanation will mainly focus on the invention made by the present inventor, and the field of application that forms the background of the invention, which is the liquid crystal driver LSI.
Although the invention has been described as being applied to, the present invention is not limited thereto. This invention includes an output circuit that simultaneously outputs a large number of signals;
The present invention can be used in general semiconductor integrated circuits having data latch circuits.

[Brief explanation of drawings]

The first wi is a block diagram of a main part showing an embodiment in which the present invention is applied to a liquid crystal driver LSI. FIG. 2 is a timing chart showing the timing of signals in each part of the circuit. FIG. 3 is a block diagram showing a configuration example of a conventional liquid crystal driver LSI. - FIG. 4 is a timing chart showing the timing of signals in each part of the LSI. SD... Output circuit (segment driver), CD...
...Output circuit (common driver), C0NT...
・Control circuit (flip-flop circuit), DLT...
Latch circuit, φW...Latch timing signal (write signal), CL...Reference signal (reference timing clock). Figure 1 Figure 2

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having an output circuit that simultaneously outputs a large number of signals and a data latch circuit, a signal serving as a reference for forming the output signal and a signal indicating latch timing. Based on this, a control circuit is provided that does not change the former reference signal while the latter latch timing signal is valid, and the output circuit is driven by the output of this control circuit. Features of semiconductor integrated circuits. 2. Where the semiconductor integrated circuit device is an integrated circuit for driving a liquid crystal display device, the semiconductor integrated circuit device is formed based on a reference timing clock formed based on an original oscillation signal and a write control signal supplied from the outside. The semiconductor device according to claim 1, further comprising a control circuit that does not change the reference timing clock based on a data latch timing signal during a period in which the latch timing signal is valid. integrated circuit. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the control circuit is constituted by a flip-flop circuit.