JPS6194926U - - Google Patents

Info

Publication number
JPS6194926U
JPS6194926U JP17756184U JP17756184U JPS6194926U JP S6194926 U JPS6194926 U JP S6194926U JP 17756184 U JP17756184 U JP 17756184U JP 17756184 U JP17756184 U JP 17756184U JP S6194926 U JPS6194926 U JP S6194926U
Authority
JP
Japan
Prior art keywords
control circuit
scale integrated
video memory
integrated circuit
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17756184U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17756184U priority Critical patent/JPS6194926U/ja
Publication of JPS6194926U publication Critical patent/JPS6194926U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案に係る大規模集積回路の一実
施例を示すブロツク図である。第2図A,B,C
は、同実施例の外観を夫々示す平面図、正面図、
側面図である。 1…映像メモリ制御回路、2…タイミング発生
回路(TG)、MC…メモリストローブ信号、Cl
ock…クロツク信号、TC…タイミング信号、3
…ライトパルス発生回路(WPG)、AB…アド
レスバス、DB…データバス、WP…ライトパル
ス、4…データ制御回路(DC)、DE…データ
制御信号。
FIG. 1 is a block diagram showing an embodiment of a large-scale integrated circuit according to the present invention. Figure 2 A, B, C
are a plan view and a front view showing the appearance of the same example, respectively;
FIG. 1...Video memory control circuit, 2...Timing generation circuit (TG), MC...Memory strobe signal, Cl
ock...clock signal, TC...timing signal, 3
...Write pulse generation circuit (WPG), AB...Address bus, DB...Data bus, WP...Write pulse, 4...Data control circuit (DC), DE...Data control signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 端末装置等における映像メモリ制御回路をゲー
トアレーに組み込み集積化してなることを特徴と
する大規模集積回路。
A large-scale integrated circuit characterized by integrating a video memory control circuit in a terminal device, etc. into a gate array.
JP17756184U 1984-11-22 1984-11-22 Pending JPS6194926U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17756184U JPS6194926U (en) 1984-11-22 1984-11-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17756184U JPS6194926U (en) 1984-11-22 1984-11-22

Publications (1)

Publication Number Publication Date
JPS6194926U true JPS6194926U (en) 1986-06-19

Family

ID=30735130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17756184U Pending JPS6194926U (en) 1984-11-22 1984-11-22

Country Status (1)

Country Link
JP (1) JPS6194926U (en)

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