JPS6194299A - Associative memory - Google Patents

Abstract

PURPOSE:To attain the collection of garbage in a single cycle by giving an access to a memory for undesired data in the same cycle for the access of a memory for desired data through an address decoder. CONSTITUTION:The 1st (p) channel FET 10 is provided together with the 1st (n) channel FET 11, the 2nd (n) channel FET 12, the 2nd (p) channel FET 13, the 3rd (p) channel FET 14 and an NOR circuit 15. The same circuit is con nected to all word lines. These word lines are driven with no invention of an address decoder according to the information on the word line to which an access is given precedingly by a cycle as well as the address information obtained from the detection of the coincidence. Thus the garbage can be col lected in a single cycle by giving the access to two word lines in the same cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an associative memory device that performs garbage collection.

The conventional structure and its problems are associated with each other. Match detection and reading are performed in memory, and when the data is no longer needed, the used area of the memory is organized and the unused area is increased to make effective use of the memory. This kind of processing is called garbage collection.

FIG. 1 shows a conventional circuit. Assume that data has been written in order from memory Mn at address 0 to memory Mn at address n, and now the data in memory lJMi at address i is no longer needed. When performing garbage correction in this circuit, address decoder 1 cannot access two or more addresses at the same time, so in the first cycle, address decoder 1
Then, inverter 3 sets word line Wn to high potential and reads out the data in memory Mn at address n to focus lines B and B. In the next cycle, address decoder 1 and inverter 2 set word line Wi to high potential. Bit I
l! Write the data of B and B to memory Ml at address 1. As described above, in the conventional circuit, two cycles are required to perform garbage correcting, and there is a problem in that high-speed processing cannot be performed.

OBJECTS OF THE INVENTION The present invention aims to eliminate these conventional drawbacks and provides an associative memory device that has a simple configuration and performs garbage collection at high speed.

Structure of the Invention The content addressable memory device of the present invention is configured so that a word line can be driven without using an address decoder using information on a word line accessed one cycle before and letter address information obtained by coincidence detection. The address decoder can drive another word line in the same cycle when one word line is being driven, and can perform garbage collection at high speed.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Second
As shown in the figure, the present invention includes a first P-channel FET.
10S first n-channel FET11, second (7)
N-channel type FET 12, second P-channel type F
ET1s, third P-channel type FET14 and NOR
It consists of circuit 16, and the same circuit is attached to all word lines.

Suppose now that the data in the memory M1 at address 1 is read out or a match is detected, and the data in the memory Mi is no longer needed. Address information when reading data from memory M1 is transmitted via n-channel FET 17 to control signal Φ2.
is held in the NOR circuit 160 input when it is at high level,
On the other hand, when matching data of memory Mi is detected,
The address information is transferred from node 18 to the n-channel FET.
1e, when the control signal Φ2 is at high level, NOR
It is captured and held at the circuit 160 input. In order to write the data of the memory at address n into the memory M1 at address 1, first, the address decoder 1 sets the word line Wn to a high level. At this time, the control signal ψ1 is at high level. When the data in the memory at address n is read out and the bit lines B and B have reached appropriate potentials, the control signal Φ1 is set to low level, and as described above, the data is held at the input of the NOR circuit 16. Because of the signal, the output of the NOR circuit 16 is at a low level and the P-channel type FET 14 is in an on state, so the word line Wi becomes a high level.

At this time, the word line W1<! - Address decoder 1 is disconnected.

Then, the data on bit lines B and B are written into memory Mi. The voltage waveforms of various parts at this time are shown in FIG. 3. By accessing two word lines in the same cycle in this way, garbage collection can be performed in one cycle.

Effects of the Invention As described above, the present invention is configured to hold memory address information that is no longer needed in advance so that word lines can be accessed without going through an address decoder. By accessing memory for unnecessary data in the same cycle as accessing memory for necessary data, garbage collection can be performed in one cycle, which is extremely effective in practice compared to the conventional two-cycle method. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional memory device, FIG. 2 is a circuit diagram of a memory device according to an embodiment of the present invention, and FIG. 3 is a graph of voltage waveforms at various parts thereof. 1...Address decoder, vDD...
・Power supply, Wi, Wn...Word line, Mi, M
n-...Memory, B, B...Bit line. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure ! Figure 2

Claims (1)

[Claims] It has an address decoder, a memory cell matrix, a word-by-word coincidence detection circuit, and an address encoder;
A source of a P-channel field effect transistor (hereinafter a field-effect transistor is abbreviated as FET) is connected to a high potential power supply, and a drain of the first P-channel FET and a drain of the first n-channel FET are connected to each other. the source of the first n-channel FET and the drain of the second n-channel FET are connected to the word line, the source of the second n-channel FET is connected to a low potential power supply, and the source of the first n-channel FET is connected to the low potential power supply; Address signals are applied to the gate of the first P-channel FET and the gate of the first N-channel FET.
The output of the decoder is connected to the second n-channel type F.
A control signal line is connected to the gate of the ET, the source of the second P-channel FET is connected to a high potential power supply, and the drain of the second P-channel FET is connected to the source of the third P-channel FET. Then, the drain of the third P-channel FET is connected to the word line, and the information of the address whose coincidence was detected one cycle ago and the information of the word line driven one cycle ago are input to the NOR circuit, and the connecting the output to the gate of the third P-channel FET;
A content addressable memory device characterized in that the control signal line is connected to the gate of the second P-channel FET.