JPS6191965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To produce a new type transistor by a method wherein a secondary carrier to be stored in a potential well produced by hetero junction of semiconductor or any other junction corresponding thereto is shifted to adjoining potential well. CONSTITUTION:In order to control the secondary electronic gas in a potential well, the proper film pressure (d) of an N type AlxGa1-xAs 20 is selected and a gate electrode 19 for Schottky junction is provided. On the other hand, a source electrode 18 ohmic-connecting to the secondary electrons in the potential well, a buried layer AlxGa1-xAs 24 and a drain electrode 17 ohmic-connecting to the secondary electrode gas in another potential well are respectively provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to ultra-high speed transistors, and particularly to a new type of transistor having a superlattice structure suitable for high integration and having high load driving capability.

(Background of the Invention) In recent years, due to the limitations of the physical constants of Si, ultrahigh-speed devices using compound semiconductors based on gallium-arsenide (GaAs) have been developed without changing the essential mechanism of transistor operation. Among them, Ga
A selectively doped heterojunction field effect transistor using a two-dimensional electron gas accumulated at the heterojunction interface between A s and A Q *G a , -, As as an active layer [for example, in JP-A-55-132074, etc. [reported] is G
Since the high mobility unique to a A and s can be utilized for FET operation, a very high-speed switching element can be constructed.

However, using this transistor, highly integrated L5
I (Large Scale Integrated
It has become clear that the disadvantage of configuring the C1rcuit is that the operating speed becomes slow. The main reason for this is the lack of load driving ability due to the small drive current. On the other hand, as a transistor with a high load driving ability, a hetero bipolar transistor in which an emitter and a base are formed by a heterojunction has been known for a long time (for example, Japanese Patent Laid-Open No. 49-43583).

However, hetero bipolar transistors have disadvantages in that the process technology required to achieve high speed is complicated, and the power consumption per ligator is high, making them unsuitable for high integration.

[Purpose of the invention]

An object of the present invention is to provide a new type of field effect transistor having a superlattice structure that is suitable for high integration and has high load driving capability.

[Summary of the invention]

Recent advances in ultra-thin film crystal growth technologies such as molecular beam epitaxy (MBE) and metal organic pyrolysis (MOCVD) have made it possible to grow crystals with controllability at the single atomic level. Using growth techniques, it has become possible to create artificial crystals with a so-called superlattice structure. Recently, devices using such artificial superlattice structures have been proposed.

The present invention is directed to a two-dimensional shape stored in a potential well (a potential well that confines electrons or holes, often becoming a quantum well potential when a heterojunction is used) created using a semiconductor heterojunction or a junction similar thereto. A new type of transistor is provided that operates as a transistor by moving carriers to adjacent potential wells.

Next, in order to explain the principle of the present invention, G a A s/
A superlattice structure consisting of five layers using AQ, Gan-, As (0<x≦1) heterojunction system is introduced. In Figure 1,
n-type A Q *G a x-wA s (x-0-3)
” / Undoped G a As 21 / P type A
Q, Ga, -, As(y~0,4) 22
/Undoped G a As 23 /n-type A (l
t G az -t A s (z ~ O-3)
In the diagram 0 showing the energy band structure of 24, AQ, Ga,
−, the difference in electron affinity between As and Ga As is ΔE1
! The energy difference at the edge of the single valence band is indicated by ΔEv, and the Fermi level is indicated by E. Do not intentionally contain impurities (
(i.e., undoped) G a As lfJ 21 ,
The film thickness of Lc-P type (or undoped) AQ, Ga□-, and AsWJ22 is Lll.

As is well known, the difference in electron affinity ΔEc (Afl mixed crystal ratio X ~ 0
．． The two-dimensional electron in the potential well 25.26 surrounded by n
Type A (I* G a 1- g A 8 layers 20°24
localized on the heterojunction interface side (Lt+Lc is approximately 40
(in the case of 0 Å or more), it is localized at energy levels throughout the entire region in undoped Ga As.

(When Ll-Lc is approximately 400 Å or less) In this unique system, the electron mobility along the heterojunction interface is less affected by impurity scattering, so the high mobility unique to GaAs is realized. can.

By the way, the two-dimensional electron gas stored in the two potential wells 25 and 26 is transferred from one well 25 to the other well 2.
If it can be moved to 6, it will be p-type AQyGan-yA.
A vertical high-speed device in which the sAs2O3 elapsed time is the main delay time can be expected.

The main reason for this is that the vertical film thickness controllability of MBE, OM-VPE, etc. is extremely good, so L, L, Lo can be controlled to be extremely thin. The key point lies in the transistor structure that embodies the method of transferring two-dimensional electrons in one well to the other well.

FIG. 2 shows an example of a transistor structure constituting the present invention.
In order to control the two-dimensional state gas in the potential well 25, the film thickness d of the n-type layer Q, Ga, -mA s 20 is
Select gate metal fi1 appropriately and make Schottky junction.
9 will be provided. On the other hand, it has a source electrode 18 that makes an ohmic connection with the two-dimensional electrons in the potential well 25, has a buried n-type layer Q++Ga1-t-A+24, and makes an ohmic connection with the two-dimensional electron gas in the potential well 26. 10 in the figure, which is a field effect transistor having a drain electrode 17, is a semi-insulating GaAs substrate.

Juttokey gate metal as n-type layer Q, Ga, -, A
When provided in the s-layer 20, the n-type layer n, Gal-mA
The two-dimensional electron gas in the potential well 25 disappears depending on the film thickness d of the s-layer 20 (enhancement type,
There are two types of normal FE: E-FET (abbreviated as E-FET) and storage type (depression type, D-FET).
Same as T.

Energy band diagrams below the gate electrodes of D-r/ET and E-FET are shown in FIGS. 3(a) and 3(b), respectively.

The operating principle of the transistor of the present invention has been explained with reference to a control electrode using a gate metal that forms a Juttky junction. However, in order to operate the transistor of the present invention,
It does not have to be a Juttokey gate electrode, and (I) p
Junction gate structure using -n junction, (2) gate structure in which a p-type layer is placed between the Schottky metal and the n-type semiconductor layer, (3) M I on the n-type semiconductor layer via an insulator. S (Metal-Ins
Basically, any electrode can be used as long as it can control a two-dimensional carrier, such as (4) a structure in which an ohmic electrode is provided directly on the n-type semiconductor layer. This is the case with various improvements made to field-effect transistors. Which electrode structure to choose depends on the specific purpose for which the transistor of the present invention is applied.

Furthermore, the transistor of the present invention can be operated using two-dimensional holes as carriers by selecting materials. For example, FIG. 4 shows an energy band diagram constituting the transistor of the present invention when a GaAsu-, P, /GaAs heterojunction is used.

That is, it has a five-layer superlattice structure, p-type aaAst-, Pm6
0/Undoped GaAs 61/n-type (or undoped) GaAs, -, P, 62/Undoped GaAs 63/n-type GaAs1-
, P, 64, which forms a potential 65.66 that confines a two-dimensional hole based on the energy difference ΔE at the edge of the hexavalence band, which shows the energy band diagram of 64, and one well 65
The transistor of the present invention can be constructed by moving the two-dimensional holes in the potential well 66 to the other potential well 66.

E in the figure indicates the Fermi level.

[Embodiments of the invention]

Hereinafter, the transistor of the present invention will be explained in more detail through examples.

Example 1 Figures 5(a) to 5(e) show the manufacturing process of an example in which a two-dimensional electron gas is used as a carrier.

On a semi-insulating GaAs substrate 10, a ζN GaAs layer 11 (undoped GaAs layer) which was not intentionally doped with impurities of 1 μm was grown at a substrate temperature of 650° C. using the MBE (molecular beam epitaxy) method. This was provided to minimize the influence of the substrate 10 on the subsequent growth.
Subsequently, an undoped AQ*Ga1-mA s layer 12 with a thickness of 500 nm is not essential for transistor operation.
Undoped Ga for human growth and prevention of surface oxidation
Achieved growth of 50 people in the top 3 of the A s layer. The undoped layer grown here uses the GaAs layer 11 as a buffer layer, but this portion is undoped AQ, Ga1. As (x~0
．． 3) Selective ion implantation is performed using the photoresist 26 as a mask to form a zero-order drain region, which may be a layer (FIG. 5(a)). The ion implantation was carried out using Si27 at an acceleration voltage of 40 kV and a dose of lXl0"an-". "After removing the photoresist, annealing was performed at 750° C. for 20 minutes in an As atmosphere to activate the implanted Si atoms 24. Furthermore, undoped Ga As
III After growing 23 to 400 people, Undope A Qy
After growing 20 Ga at-yA s (y-0,4) layers 14, a p-type AQ, Ga, -, As (y~0.4) layer 22 doped with Be I x 10"C1m-" is grown. 5
After the growth of 0 people, undoped AQyGa1-yAs(y~0
．． 4) Growth of layer 15 by 20 people. Undoped A Q, G
The al-yAs layers 14 and 15 are inserted for the purpose of preventing a decrease in mobility. Furthermore, undoped GaAs layer 21 was formed by 400 layers, undoped AQ, Gax-As (z
~0.3) Layer 16 by 50 people and further Si by I
0"css-" doped A Q s G a 1-
*A After growing 8 layers and 20 people for 350 people, ultra-high vacuum (I0-
2,000 M o 19 were grown in a separate room inside the '''torr (Figure 5(b)).

Next, in order to make an ohmic connection to the zero-order drain region 24, which was selectively etched using a mixed gas of NF3 and He gas so as to leave the gate electrode portion using a photoresist as a mask, first, the epitaxially grown layer 20,
16, 21, 15°22.14 were chemically etched (
(Fig. 5 (C)), then 3000 people deposited KSiO, 30 on the entire surface using the C, VD method (Fig. 5 (c)), CVD 5i0
．． 30 was selectively removed using an araric acid-based etching solution to form source/drain electrodes 18 and 17 (see Figure 5(d)).
)) At this time, A is used as the source/drain electrode metal.
1200 people/200 people/2000 people of uGe/Ni/Au were vacuum-deposited, respectively.

A plan view of this embodiment is shown in FIG. 5(e). The part indicated by the dotted line 25 is the intrinsic transistor region, and the other part is the p-type layer (
! The concentration of p-type dopant in yG al-yA s 22 is the threshold voltage of the transistor.

In order to control the electron concentration confined in the potential, a wide range (I0°Ql −” to 10″aI−
). Also, the external electrode and this p-type layer 41
．． It is also possible to connect G at- and A s 22 and use it as a control terminal for vertical current.

In this embodiment, a Schottky junction is used for the gate electrode 19, but (I) a p-type layer a/'- is formed between the Schottky metal and the n-type layer QGaAs 20.
The logic amplitude may be increased by inserting an s- or p-type layer F, GaAs, or a gate electrode structure may be formed that is ohmically connected to the p-type layer. Alternatively, an ohmic electrode may be used instead of the gate electrode.

Example 2 An example in which an enhancement type transistor (E type) and a depletion type transistor (D type) were created on the same substrate is shown in the sixth example.
Shown in Figures (a) and (b).

Drain regions 24 for E type and D type are respectively provided in the same manner as in Example 1, using undoped A (I, Ga, -, As16* grown by MBE method, and then n type Afl containing 1 x 101 m of Si). , 250 Gat-mAs layers 20 were grown, and then 250 n-type layers aAsp 9 with the same doping amount were grown (FIG. 6(a)).

Next, in order to take out the electrode for ohmic connection to the drain region, a part of the grown layer was removed by chemical etching using the photoresist 26 as a mask, and a
Human Si0.30 was deposited.

Next, in the case of an E-type transistor, the n-type GaAs layer 9 is selectively etched using a mixed gas of CCU, F, and He, and after heating at 400°C for 30 minutes, the gate metal Ti
/Pt/Au19' was vacuum deposited. Next, the gate metal of the D-type transistor Ti/Pt/
Au (I000 people 7200 people / 1000 people) 19
was similarly deposited. After that, as in Example 1,
A drain electrode was formed.

Example 3 A manufacturing example using a three-dimensional hole gas as a carrier is shown in the seventh example.
As shown in the figure.

An undoped GaAs layer 11 is grown to a thickness of approximately 1 μm on a semi-insulating GaAs substrate 10 using the MBE method.

Furthermore, 500 GaAs, P, (z=0.3) layers and 30 undoped GaAs layers 71 were grown.

Here, the undoped GaAs layer 11 is introduced to eliminate the influence of the substrate, and is not essential for transistor operation. To form a drain region, Mg ions 91 are heated at an acceleration voltage of 100 kV,
Ion implantation was performed at a dose of x 10"cm-". After removing the photoresist, lamp annealing was performed at 850°C for 10 seconds in an As atmosphere to activate Mg atoms 92 (7th
Figure (a)).

Further, using the MB method, 200 layers of undoped Ga As layer 63 were formed, and undoped Ga PI-yA 8 y (
'j = 0.4) for 10 people, Si for 2 X I Qt
N-type layer included in tal-3 a P 1-yA Sy (
3' = 0-4) for 100 people, undoped゛Ga
Px-yA! Iy (y = 0-4) for 10 people,
200 undoped GaAs, undoped GaP,
-As, (x=0.3) for 10 more people, Mg for IX
10"Ql-" P-type GaP1-, A8. (X=0.
3) is formed by 500 people at the zeroth order T i / P t /
Au19 was deposited in an ultra-high vacuum (I0-''Torr) at 1000 people, 400 A, and 1000 people, respectively (Fig. 7(b)
).

The following activation process was carried out almost in the same manner as in Example 1 to form source/drain regions and source/drain electrodes. However, this time, Cr--Au was used as the electrode metal in order to make ohmic contact between the p-type semiconductor and the two-dimensional hole gas.

In the above embodiments, the semiconductor layer sandwiched between the two-dimensional carriers is an example in which semiconductor layers of different conductivity types are used in the two-dimensional carriers, but this is not necessarily necessary for transistor operation. The same conduction type is sufficient.

Embodiment 4 In the above embodiments, an embodiment using a Schottky junction gate electrode has been described, but the transistor of the present invention can also be constructed using an MO5 type or MIS type gate structure.

FIG. 8 shows an example using InP/InGaAsP.

4000 layers of undoped InP were formed on a semi-insulating InP substrate 30 by the MoCVD method, and Si ion implantation 31 was performed using the photoresist 26 as a mask to form an n-type layer at a dose of 100 b V 2 X 10"cs+-". After forming a layer 32 (FIG. 8(a)), the substrate was subsequently cleaned and light etched, and then an undoped InGaA layer was formed.
200 people used sP34, and 200 people used n-type InP35 doped with 1×10'''01''1 Si.

200 undoped InGaAsP36, 5 Si
700 x 10"am-" doped n-type InP37
Made people grow. Next, the InP was oxidized by plasma anodic oxidation to form an oxide 38 (FIG. 8(b)).

Next, as in Example 1, source 18. A drain 17 and a gate 19 were formed (FIG. 8(c)).

In addition to the above embodiments, heterozygous systems in which the present invention can be practiced include A flyG a,-, As-A QmG ax-
, AseGaAs-AQGaAsP, InP-I
nGaAs*I nAs-GaAs layer 11. AI',
Ga1. , As-Ge, GaAs-Ge, C:dTe
InSb.

Possible examples include Ca5b-1nAs.

Example 5 Another example of forming the n-type buried region 24 in Example 1 is shown in FIG.

Using the MBE method on the semi-insulating GaAs substrate 10, p-(doping level I
After growing 5,000 GaAs layers 11 (around ``Ql-''),
p- (doping level 1 x 10 cm -' around) A
l1. Ga,-,AsJFJ(x~0.3) 12 was grown at 500A. Next, using the ion beam lithography equipment in the MBE* equipment, Si ions were irradiated at 100 hv.
An n-type buried layer 24 was formed in a region of a desired shape (in a plane) at a dose of 5 x 10"(!l-").Subsequently, annealing was performed at 800°C for 15 minutes in an As# atmosphere for implantation. After forming the activated buried layer, the present invention was carried out in the same steps as in Example 1.

〔Effect of the invention〕

The effects of the present invention can be summarized as follows.

Two potential wells are set between the heterojunction interface or a similar interface, and the structure is such that a current is extracted between them in the in-plane vertical direction. Lo
In the case of n, the thickness between the potential wells is a, and the gate length L
g, it was possible to extract a current that was approximately 'L g/a times.

[Brief explanation of drawings]

1riA is an energy band diagram for explaining the operating principle of the transistor of the present invention, FIG. 2 is a diagram showing the cross-sectional structure of the transistor of the present invention, and FIG. 3 is a diagram showing the operating principle of the depletion type and enhancement type transistors of the present invention. Figure 4 is an energy band diagram of a transistor when a two-dimensional hole gas is used as a carrier, and Figure 5. 6th. 7th.
FIG. 9 is a diagram showing an example of the manufacturing process of a transistor of the present invention, and FIG. 8 is a diagram showing an implementation process of the present invention using an MO3 type gate structure. 24, 20, 6
1゜63・=n'1jlAn, Ga1-, As layer, 21
, 23... Undoped G'aAs layer, 22... p-type or undoped All, Ga1-, As layer, 19...
・Gate electrode, 30 ... Interlayer insulator, 60.64-
p-type GaAs, -mPm layer, 62- n-type or undoped GaA31-y P y. 24...Si atom, 27...Si ion beam, 2
5... Inter-element isolation region, 26... Photoresist,
91st /I! 1 2nd mill 3rd 4th figure z4 6th mouth 7th eye 7th eye -

Claims (1)

[Claims] Based on the respective layer structures of the first, second, third, fourth, and fifth consecutive semiconductor layers, the electron affinities of the second and fourth semiconductor layers are the same as those of the first and third semiconductor layers. , or the energy at the valence band edge of the second and fourth semiconductor layers is greater than the energy at the valence band edge of the first, third and fifth semiconductor layers, The first electrode controls the carrier in the potential well (I) formed by the first and third semiconductors.
In addition, a potential well (I) is formed in the semiconductor layer of
an electrode electrically connected to the carrier in the potential well (II) formed by the third and fifth semiconductors; The carrier in the well (I) is converted into a potential well (
II) A semiconductor device characterized by being moved to the side. 2. The first and fifth semiconductors are n-type semiconductors, and the second and fourth semiconductors are not intentionally doped with impurities (undoped; carrier concentration of 10^1^5 cm^-^3 or less). A semiconductor device according to claim 1, characterized in that: 3. The semiconductor device according to claim 1, wherein the first and fifth semiconductors are p-type semiconductors, and the second and fourth conductors are undoped. 4. The semiconductor device according to claim 1, wherein Al_xGa_1_-_xAs is used as the first, third, and fifth semiconductors, and GaAs is used as the second and fourth semiconductors.