JPS6191756A - Control system for buffer memory in input and output controller - Google Patents

Abstract

PURPOSE:To buffer storage length data of optional length by stopping data reading operation from a buffer memory when a final data flag bit is detected. CONSTITUTION:When data is written on a magnetic tape device (MTU)5 from a channel device (CH)3, an input/output controller 4 receives a write command and sets the next address of a final data address in a buffer memory address register 29. Then, CH3 sends data, which is stored in the buffer memory; 23. When final data of one record length is sent, '1' is sent as a final data indica tion signal together with the data. Consequently, the final data flag in the buffer memory is set to '1'. When the buffer memory 23 becomes full, reading opera tion is started and one transfer data is read out of the buffer memory 23. At this time, only the data part in a B data register 24 is sent to MTU5. Then, when the final data flag is '1', transfer to MTU5 is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a buffer memory control method in an input/output control device.

(Prior Art) It has been well known to place a buffer in an input/output control device. This buffer memory amount is generally selected to be one transfer data amount or one recording unit length.

Particularly in magnetic tape control devices, the amount of data transferred per transfer is selected. This is because one recording length is taken into consideration so that only the necessary amount can be recorded without depending on the amount of buffer memory. However, this method has a technical drawback in that data must be transferred at a high speed matching the recording speed of the magnetic tape device.

Furthermore, when two buffer memories for one transfer amount of data are provided, there is a disadvantage in that the technique becomes complicated because the buffer memories are switched and used at high speed within a transfer unit time.

Further, when a pack 7 memory having a capacity of one recording unit length is provided, data in the buffer memory is sent to a host device or a magnetic tape device by detecting that the buffer memory is full. In this case, if data with a recording unit length that is less than the capacity of the backup memory is transferred, the fullness of the backup memory will not be detected, and the data will not be transferred normally. That is, it has the drawback that only data with a recording unit length equal to the capacity of the buffer memory can be transferred at all times.

(Object of the Invention) An object of the present invention is to provide a buffer memory control method in an input/output control device that solves the above-mentioned drawbacks by having a final data flag bit for every ≠1 transfer data length.

(Structure of the Invention) According to the present invention, in an input/output control device having a buffer memory for storing data from a channel device or an input/output control device of one recording length or more, a final data file is stored in the backup memory for each transfer data. Part f that stores bits
A buffer memory control method for an input/output control device, characterized in that the data read operation from the buffer memory is stopped when the flag bit is detected in the data read operation from the backup memory. An embodiment of the present invention will now be described with reference to the drawings. FIG. 1 is a system configuration diagram of an example of an apparatus to which the present invention is applied. The channel device 3 is connected via a path line 10 to an input/output control device 4.6. The input/output control device 4 is a magnetic tape control device and controls the magnetic tape device 5 via the bus line 11.

Similarly, the input/output control device 6 is a line printer control device that controls the line printer 7t.

The central processing unit 2 is connected to the main memory 1 and the channel device 3, and reads, decodes, and executes instructions stored in the main memory 1. If the instruction is an input/output instruction, channel device 3
1: Start. The activated channel device 3 takes out the PiO command from the main storage device 1 and sends it to a specific input/output control device. Thereafter, the channel device 3 starts data transfer with the input/output control device.

The input/output control device 4 will be explained below. FIG. 2 is a block diagram of one embodiment of the input/output control device 4 in FIG. 1. Second
The figure shows the bus line 10 in FIG. 1 divided into 10-1 and 10-2. Similarly, the bus line 11 in FIG. 1 is also shown divided into 11-1 and 11-2 in FIG.

The cable receiver 21 receives the path fR1 from the channel device 3.
It receives the data sent out through lines 0-1 and the final data instruction signal, and sends them out to the selection circuit 22 through the signal line 50. The cable receiver 27 is a magnetic tape unit (hereinafter MTU).
, abbreviated as) 5 via the bus line 11-1, and sends it to the selection circuit 22 via the signal line 54.

The W data register 28 sends the set data to the selection circuit 22 via the signal line 55't-.

The selection circuit 22 is connected to the buffer memory 23 via a signal line 51'ii-. The read data of the buffer memory 23 is sent to the R data register 35 via the signal line 52.
and is sent to the B data register 24.

The most significant bit 80 in the B data register 24 indicates the detection of the final data flag signal via the signal line 90t.
Inform PU30. The circuit for informing is omitted with 1 moe.

The data in the B data register 24 is sent via signal line 53 to cable drivers 25,26. Cable driver 25 sends the data on signal line 53 to bus line 10-1. Cable driver 26 sends the data on signal line 53 to bus line 11-1. CPtJ 30 is called a microprocessor and has read-only memory 31 . Read/write memory 32. W data register 28. Buffer memory address register 29
, R data register 35. Channel control register 33
, MTU control register 34. CPU3
0 can be written to the W data register 28, readable and writable to the buffer memory address register 29, readable to the 几data register 35, and can be written to the channel control register 33. MT
The U control register 34 can be read and written.

Buffer memory address register 29 is connected to buffer memory 23 via signal line 56 .

Buffer memory address register 29 is an increment register that indicates the address of data to be stored in buffer memory 23 or the address of stored data. Channel control register 33 is a register that transmits and receives control data to and from channel 3 in FIG. 1 via signal line 10-2. Similarly, the MTU control register 34 also has the MTU control register 34 in FIG.
5 through the signal line 11-2.

FIG. 3 is a block diagram of the buffer memory. Section F of the buffer memory is a final data flag pit. "0" is written for data other than the final data, and "1" is written for the final data. Portion D of the back 7 memory is a portion that holds one transfer data. record 0
．． Record 1,..., record n indicates one record length, l
This shows that it is possible to hold multiple pieces of record length data.

Next, based on this embodiment, the operation when writing from the channel device to the MTU will be explained with reference to FIG. 82. When the input/output control device 4 receives the write command, it sets the address next to the final data address in the buffer memory address register 29. It is automatically set except for special conditions such as when an error occurs. Also, during initial settings, it always indicates the beginning of the buffer memory.

When data is sent from that channel via the bus 510-1, the selection circuit 22 sends the data on the signal aso to the signal line 51. The data on signal line 51 is stored at the address indicated by buffer memory address register 29. At this time, the final data instruction signal is set to "0", and rOJ is stored in the final data flag bit in the buffer memory.

Thereafter, the buffer memory address register 29 is incremented. Next, when data is sent from the channel, it is stored in the buffer memory 23 in the same way as above. Regarding the final data of 0 1 recording length, rlJ is sent from the channel as the final data instruction signal together with the transfer data. . At that time, "1" is stored in the final data flag bit in the buffer memory.

In this way, data of l record length is stored in the back memory. This operation continues until the buffer memory is full or a command other than write is received from the channel.

When the buffer memory becomes full, the CPU 30 temporarily suspends data transfer with the channel and shifts to a read operation of the buffer memory 23. That is, a read address is set in the buffer memory address register 29 and a read operation is performed. When one transfer data is read from the buffer memory 23, it is set in the B data register 24, and only the data part is sent to the MTU via the signal line 53 and the bus line 11-1. Thereafter, the buffer memory address register 29 is incremented. This operation continues until the final cheetah flag pit is detected.

When the final data flag bit is detected, it is notified to CPU 30 via signal line 90. The CPU 30 sends the final data to the iMTU and at the same time sends the final data to the MTU control register 3.
4 to notify the MTU of the stop. In this way, one recording length of data is recorded on the tape.

If data to be recorded on the tape remains in the buffer memory, the recording continues until there is no more data to be recorded on the tape. When all the data is gone, the CPU 30 releases the hold on data transfer with the channel. In this way, the write operation to the MTU continues.

Next, the case of read operation from the MTU will be explained with reference to FIG. When the input/output control device 4 receives the read command, it sets address data in the buffer memory address register 29 and activates the MTU. MTU reads the data on the tape and connects it to the bus! 11-1', data is sent to the input/output control device 4. The selection circuit 22 in FIG. 2 sends the data on the signal line 54 to the signal line 51.

The data on signal line 51 is stored at the address indicated by buffer memory address register 29. At this time, the final data flag bit of data other than the final data of one recording length is stored as "O".

Next buffer memory address register 29 is incremented. This operation continues for one record length.

When the last data of one recording length is reached, a final data instruction signal is sent from the MTU at the same time as the final data. When the final data indication signal is present, the final cheater flag bit is set to “1”.
" is stored. However, some MTUs do not have a final data indication signal. So CPU 30 is MTU
When the end of the read operation of one record length is detected, the contents of the buffer address register 29 are moved backward by one, the final data in the buffer memory is read, and the data register 35 is read.
At the same time, the most significant bit of the W data register 28 is completely set to "1". Reset the buffer address register 29 and press W.
The data in the data register 25 is stored in the buffer memory. This process continues until the buffer is full.

When the buffer memory is full, the data in the buffer memory 23 is read out to the B data register 24, sent to the bus line 10-1 via the signal line 53t-, and sent to channel 3 in FIG. This operation continues until the final data flag bit is detected.

When the final data bit is detected, the CPU 30 is notified via signal line 90. At the same time as sending the final data to the channel device, the CPU 30 sets stop data in the channel control register 33 and notifies the channel device. When the next read command comes, the next record in the buffer memory is sent to the channel device. When the buffer memory becomes empty, data is automatically read from the j5MTU by the CPU 30 and stored in the buffer memory IJ23K.

The case where there is one buffer memory was explained above, but when there are two buffer memories (double buffer memo I))
It is easy to understand that the same thing applies to IIC.

In this embodiment, the capacity of the buffer memory is multiplied by multiple times for one recording length, the buffer memory configuration allows writing and reading for each t-1 transfer data, and the final data flag bit is set for each transfer data. By providing
Recording of magnetic tape devices.

This solves the technical problem of having to transfer data at high speeds.

This solves the drawbacks of technical complexity due to high-speed switching and use.

Further, the recording length is not fixed, and recording lengths of arbitrary lengths can be mixed and used.

(Effects of the Invention) According to the present invention, it is possible to transfer data at a high speed matching the recording speed of a magnetic tape device, and it is also possible to use a mixture of recording lengths of arbitrary lengths instead of keeping the recording length constant. There is an effect that makes it possible.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an apparatus to which the present invention is applied, FIG. 2 is a block diagram of an embodiment of the input/output device portion thereof, and FIG. 3 is a configuration diagram of an example of a buffer memory. 1... Main storage device, 2... Central processing unit, 3...
Channel device, 4, 6... Input/output control device, 5...
Magnetic tape device, 6...Line printer, 30...Micro tea Figure 2 Figure 3

Claims (1)

[Claims] In an input/output control device having a buffer memory for storing data from a channel device or an input/output control device of one recording length or more, a portion for storing a final data flag bit for each transfer data is provided in the buffer memory, and the buffer A buffer memory control method in an input/output control device, characterized in that, in an operation of reading data from the memory, when the flag bit is detected, the operation of reading data from the buffer memory is stopped.