JPS6188640A - Digital phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the output jitter of a reproduction carrier wave by detecting a waveform distortion generated at a place near the changing point of data and suppressing the input of a modulated wave to a synchronizing circuit at the time point of said detection of the waveform distortion. CONSTITUTION:A demodulation part consists of a wave detecting/decoding circuit, a clock reproducing circuit and a carrier wave reproducing circuit. A pattern generator 25 detects a pattern which produces a phase fitter due to the waveform distortion out of the demodulated signal supplied through a terminal 26. In such a case, the input of modulation is prevented by a gate circuit 22. Furthermore the output of a phase comparator is suppressed at a place near the changing point of data by a clock signal containing the changing point of the data which produce the phase fitter due to the waveform distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital synchronous detection circuit that performs carrier wave recovery using binary quantized digital PLL.

[Conventional technology]

FIG. 1 is a block diagram of a carrier recovery circuit using a conventional binary quantization digital PLL.

In FIG. 1, a signal wave input from a terminal 1 is quantized into two values by a limiter 2.

That is, if the signal wave exceeds a certain threshold level, the signal on the signal line 3 becomes a logic "1" level, and conversely, if it is below a certain threshold level, it becomes a logic "0" level.

The phase comparator 4 compares the phases of the regenerated carrier wave and the human signal wave, and when the signal wave is in a phase that is ahead of the regenerated carrier wave, the signal is sent to the signal line 5, and when it is in a delayed phase, it is sent to the signal line 6. Outputs a delayed signal. The sequential filter 7 is a counter that performs cutting based on the leading signal and subtracting based on the delayed signal. When the counted value exceeds a certain value, it sends a delayed control signal to the signal line 8, and when it falls below a certain value, it advances to the signal line 9 and outputs the control signal. do.

The phase controller 10 adds one pulse to the high-speed (higher frequency than the reproduced carrier wave) clock input from the terminal 11 when the lead control signal is input, and adds one pulse when the delay control signal is input.
Controls pulse deletion and outputs to signal line 12. The divider 13 divides the high-speed clock signal output from the phase controller 10 to the same frequency as the reproduced carrier wave. The frequency division number determines the amount of phase control per time.

Therefore, a reproduced carrier wave having a phase error determined by the frequency division number of the frequency divider 13 is outputted to the terminal 14.

[Problem that the invention seeks to solve]

In such conventional circuits, when used in a transmission line that causes waveform distortion due to a filter or the like that causes phase jitter larger than normal white noise, it is necessary to greatly reduce the number of sequential filter stages. However, although increasing the number of stages of the sequential filter reduces the phase jitter of the recovered carrier, it also has the disadvantage of narrowing the synchronization pull-in range.

In order to solve these drawbacks, the present invention detects the waveform distortion that occurs near the data change point and suppresses the output of the reproduced carrier wave by a method such as suppressing the input of the modulated wave at that time to the synchronization circuit. The aim is to reduce the

EMBODIMENT OF THE INVENTION Hereinafter, the structure etc. of this invention will be described in detail based on the drawing of an Example.

〔Example〕

FIG. 2 is a block diagram of the embodiment #i of the present invention, in which 1 to 14 indicate signal terminals or circuit elements similar to those in FIG. 1, and 20 indicates a quantized input signal. 21 is a signal line for the output of the delay circuit; 22 is a gate circuit that prohibits input of the delayed modulated wave to the phase comparator 4 using the pattern detection signal 24; 23 is a delay circuit that delays the wave by the time required for pattern detection; The output signal line 25 of the data 1 circuit indicates a circuit that detects a specific pattern from the decoded signal inputted from the terminal 26.

Generally, in the synchronous detection method, a demodulation section is configured by a detection and decoding circuit, a clock recovery circuit, and a carrier recovery circuit, which is the object of the present invention. The explanation here assumes that a decoded signal is obtained from a decoding circuit within the demodulation section.

In the embodiment shown in FIG. 2, a pattern that generates a phase book due to waveform distortion is detected by a pattern detector 25 from a decoded signal inputted from a terminal 26, and the modulation input at this time is suppressed by a date circuit 22. It's on.

FIG. 3 is a block diagram of a second embodiment of the present invention,
1 to 14 are the same as those in the fIS1 diagram, 30 is a date circuit, 31 is a signal line to which an advanced signal that has passed through the gate circuit 30 is output, 32 is a signal line to which a delayed signal that has passed through the date circuit is output, and 33 represents the main terminal that supplies the clock.

In FIG. 3, the lead signal and the delay signal which are the outputs of the phase comparator 4 are input to the sequential filter through the gate circuit 30, and the date circuit 30 is generated by one clock regeneration path and is input into the terminal 3. It operates to block the passage of both signals near the change point of the supplied clock. As a result, the phase comparator output near the data change point is suppressed by the clock signal that includes the data change point where phase jitter occurs due to waveform distortion.

FIG. 4 is a block diagram of a third embodiment of the present invention,
1 to 14 are the same as in FIG. 1, and 40 represents an AD converter.

The A-D converter 40 converts the input modulated wave into three values.
The converter outputs a signal to the signal line 41 to stop the evaluation phase comparison operation when the input signal level is an intermediate value.

In this embodiment, when an intermediate level is generated due to amplitude fluctuation in the modulated wave due to waveform distortion, this is the 3-value A-D
Since it is detected by the converter and its output stops the operation of the phase comparator, it is possible to reduce jitter in the reproduced carrier wave due to waveform distortion of the input modulated wave.

〔Effect of the invention〕

In a carrier regeneration circuit that extracts a carrier wave from a digitally modulated signal wave, waveform distortion caused by a band-limiting filter in the modulation/demodulation system occurs as an envelope fluctuation of the modulated wave during amplitude quantization, and as a phase change due to code amount interference during phase comparison. Each of these jitters causes an increase in the output phase jitter of the reproduced carrier wave.

In particular, a digital PLL (Phase L
When using ``Ockecl Loop'', near the data change point where the noise margin has decreased due to the above envelope fluctuation, it is likely to become ALL "1" or ALL "0", compared to phase jitter caused only by normal noise. This results in a much larger value.

Since the present invention performs phase synchronization by excluding modulated waves with waveform distortion, the sequential filter constituting the synchronization circuit can be designed for only normal white noise. Therefore, there is an advantage that both the pull-in characteristic and the jitter suppression characteristic can be satisfied with a simple filter.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a carrier recovery circuit using a conventional binary quantization digital PLL, FIG. 2 is a block diagram of a first embodiment of the present invention, and FIG. 3 is a block diagram of a second embodiment of the present invention. FIG. 4 is a block diagram of a third embodiment of the present invention.

Claims (5)

[Claims] (1) In a binary quantization digital PLL circuit that reproduces a carrier wave from a quantized digital modulated wave, when waveform distortion or a specific condition related to the generation of waveform distortion is detected, the input of the modulated wave to the phase comparator or A digital phase synchronization circuit characterized by comprising means for suppressing the output of a phase comparator. (2) The digital phase synchronization circuit according to claim (1), which detects a specific decoding pattern and suppresses input of a modulated wave including the pattern to a phase comparator or output of the phase comparison result. (3) Digital phase synchronization according to claim (1), which detects a sign change in decoded data and suppresses input of a modulated wave near the change point to a phase comparator or output of the phase comparison result. circuit. (4) The digital phase synchronization circuit according to claim (1), which suppresses the input of the modulated wave near the edge of the reproduced clock signal to the phase comparator or the output of the phase comparison result. (5) A method according to claim (1) that performs multi-level quantization on an input signal, detects an intermediate level signal, and suppresses the input to the phase comparator or the output of the phase comparator. Digital phase synchronized circuit.