JPS6187366A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6187366A JPS6187366A JP20802484A JP20802484A JPS6187366A JP S6187366 A JPS6187366 A JP S6187366A JP 20802484 A JP20802484 A JP 20802484A JP 20802484 A JP20802484 A JP 20802484A JP S6187366 A JPS6187366 A JP S6187366A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- magnesium
- aluminum
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011777 magnesium Substances 0.000 claims abstract description 51
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052749 magnesium Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 4
- 229910000861 Mg alloy Inorganic materials 0.000 claims 1
- 150000002680 magnesium Chemical class 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 36
- 239000010409 thin film Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910003023 Mg-Al Inorganic materials 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910000714 At alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- -1 Phospho Chemical class 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置及びその製造方法に係り、特に、半
導体ＩＣ（集積回路）に用いる配線金属の抵抗率を小さ
くすると同時にＳｉ面とのフンタクト抵抗を小さくする
ことを図った半導体装置及びその製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to reduce the resistivity of wiring metal used in semiconductor ICs (integrated circuits) and at the same time reduce the direct resistance with the Si plane. The present invention relates to a semiconductor device and a method for manufacturing the same that aim to reduce the size of the semiconductor device.
８１基板を用いる半導体１ｃにおいて配線金属は、Ｓｉ
面と接触させた時のコンタクト抵抗並びにＩＣ上を引き
廻した時の配線抵抗を減少させるという、両者の条件を
満たすことが必要である。In the semiconductor 1c using the 81 substrate, the wiring metal is Si
It is necessary to satisfy both conditions of reducing the contact resistance when making contact with a surface and the wiring resistance when being routed over an IC.
第５図に、従来用いられているＡ！！、 Ｔｉ 、 Ｍ
ｏ等の配線材料金属のコンタクト抵抗ρＣ及び抵抗率ρ
を示す。コンタクト抵抗ρ。とじてはこれまでに発表さ
れている文献値を用い、抵抗率ρとしてはＴｉ。Figure 5 shows the conventionally used A! ! , Ti, M
Contact resistance ρC and resistivity ρ of wiring material metal such as o
shows. Contact resistance ρ. For the final determination, the literature values published so far were used, and the resistivity ρ was Ti.
Ｍｏについてはンリサイドの場合について示す。第５図
より、現在量も多く用いられているＡ／においては、抵
抗率ρとしては最も小さく良好であるが、コンタクト抵
抗ρ。は約１０−６Ω・ｄと高い。一方、Ｔｉ、 Ｍｏ
においては、コンタクト抵抗ρ。が５ＸｌＯ−７Ω・ｄ
と十分には低くならず、しかも抵抗率ρがＴｉにおいて
は３０μΩ・（ｐ 、 Ｍｏにおいては１６μΩ・αと
Ａ／に比べ５倍以上大きな値となっている。Regarding Mo, the case of non-reside is shown. From FIG. 5, it can be seen that A/, which is currently widely used, has the smallest resistivity ρ, which is good, but the contact resistance ρ. is as high as approximately 10-6 Ω·d. On the other hand, Ti, Mo
In , the contact resistance ρ. is 5XlO-7Ω・d
Moreover, the resistivity ρ is 30 μΩ·(p) for Ti and 16 μΩ·α for Mo, which is more than 5 times larger than that of A/.
さらに、コンタクト抵抗増大の一要因となっているＳｉ
面と配線金属との間の障壁電位差φＢも、Ｎ型Ｓｉとの
接触の場合、ＡＩ、 ＭｏではφＢ＝ｏ、７ｅＶ、また
ＴｉにおいてもφＢ＝０．５ｅＶｔｉｆ後で大きな値で
ある。このため積層化により上部に厚いＡ／Ｉｌｉを堆
積して配線抵抗の減少を図ったとしても、５１面と接触
している部分のコンタクト抵抗を大幅に低減させること
はできなかったつ
〔発明の目的〕
本発明は、従来技術での上記した問題点を解決するため
になされたもので、抵抗率の特に小さいＡｔを母体とし
、これに十分少さな障壁電位差（φＢ二０．３７ｅＶ）
を持ち、かつ抵抗率（ρ＝５４μΩ・ｃｍ）の小さいマ
グネ／ラム（Ｍｇ）を一部に含ませる構造及び製造方法
としたもので、これにより微細化配線で要求される、低
コンタクト抵抗並びに低抵抗率の両者条件を満足させる
ことのできる半環ｔｉ装置δ及びその製造方法を提供す
ることにある。Furthermore, Si, which is a factor in increasing contact resistance,
The barrier potential difference φB between the surface and the wiring metal is also a large value in case of contact with N-type Si, φB=o, 7 eV for AI and Mo, and also after φB=0.5 eVtif for Ti. For this reason, even if we tried to reduce the wiring resistance by depositing thick A/Ili on the top by layering, it was not possible to significantly reduce the contact resistance of the part in contact with the 51st surface. ] The present invention was made in order to solve the above-mentioned problems in the conventional technology, and uses At as a base material, which has a particularly low resistivity, and a sufficiently small barrier potential difference (φB2 0.37 eV).
It has a structure and manufacturing method that partially contains magneto/ram (Mg), which has a low resistivity (ρ = 54 μΩ・cm) and has a low resistivity (ρ = 54 μΩ・cm). The object of the present invention is to provide a half-ring Ti device δ that can satisfy both conditions of low resistivity and a method for manufacturing the same.
ここで、上記したＭｇの小さな障壁電位差値と小さな抵
抗率値の特性を考慮すると、Ｍを用いずにＭｇのみを用
いても本発明の目的が達成できるようにも考えられる。Here, in consideration of the above-mentioned characteristics of Mg having a small barrier potential difference value and a small resistivity value, it is possible to achieve the object of the present invention even if only Mg is used without using Mg.
しかし、Ｍｇは化学反応において活性度が比較的大きな
金属であるためＭｇのみを用いるとＭｇが大気中にさら
されている構造となりＡＩ！の場合に比べて不安定とな
る。従って、本発明では、Ｍｇの上をさらにＡＩ！をも
って覆う構造、もしくはＭｇとＡＩ！とを合金化した金
属で全体を覆う（，１４造の半導体装置及びその製造方
法を採用する。However, Mg is a metal with relatively high activity in chemical reactions, so if only Mg is used, a structure in which Mg is exposed to the atmosphere results in AI! It is unstable compared to the case of . Therefore, in the present invention, AI! Structure that covers with Mg and AI! The entire device is covered with a metal alloyed with the semiconductor device and its manufacturing method.
本発明の特徴は、半導体基板表面に絶縁層を有し、この
絶縁層に開口部を有し、この開口部を介して上記半導体
基板の内部領域と電気的に連接すべく、上記絶縁層の上
面及び上記開口部に形成される導電性層を有する半導体
装置において、導電性層がアルミニウムとマグネシウム
とを含む構成とすることにある。The present invention is characterized by having an insulating layer on the surface of the semiconductor substrate, having an opening in the insulating layer, and connecting the insulating layer electrically to an internal region of the semiconductor substrate through the opening. In a semiconductor device having a conductive layer formed on the upper surface and the opening, the conductive layer contains aluminum and magnesium.
具体的な構成としては、導電性層が、開口部に充填され
かつ絶縁層の上面に形成された薄いマグネシウム膜と、
このマグネ／ラム膜を覆って形成された厚いアルミニウ
ム膜との２層（１４造から成る構成、あるいは、開口部
の半導体基板表面と接する側にのみ形成された薄いマグ
ネシウム膜と、このマグネシウム膜の上面及び絶縁層の
上面を覆って形成された厚いアルミニウム膜とから成る
構成、あるいは、導電性層がマグネシウムとアルミニラ
ｉｃｌの具体的（、“４成を得るために、半桿体ＪＪ：
、仮表面に絶縁層を形成する工程と、この絶縁層の所定
の位置１こ開口部を設ける工程と、この開口部にのぞむ
上記半導体基板表面と、上記絶縁層の上面及び開口側端
部を葭って薄い第１のアルミニウム層を形成する工程と
、この第１のアルミニウム層を覆ってマグネシウム層を
形成する工程と、このマグネシウム層を覆って第２のア
ルミニウム層を形成する工程と、所定の温度でアニール
することにより上記第１及び第２のアルミニウム層及び
マグネシウム層を合金化させて導電性層を形成する工程
とを含む製造方法とするにある。Specifically, the conductive layer includes a thin magnesium film filled in the opening and formed on the top surface of the insulating layer;
A two-layer structure with a thick aluminum film formed covering this Magne/RAM film, or a thin magnesium film formed only on the side of the opening in contact with the semiconductor substrate surface, and a thin magnesium film formed only on the side of the opening in contact with the semiconductor substrate surface. A structure consisting of a thick aluminum film formed over the top surface and the top surface of an insulating layer, or a structure in which the conductive layer is made of magnesium and aluminum ICl ("4", semi-rod JJ:
, a step of forming an insulating layer on a temporary surface, a step of providing an opening at a predetermined position in this insulating layer, and a step of forming an opening on the surface of the semiconductor substrate looking into the opening, and a top surface and an end of the insulating layer on the side of the opening. a step of forming a thin first aluminum layer by covering the first aluminum layer; a step of forming a magnesium layer covering the first aluminum layer; a step of forming a second aluminum layer covering the magnesium layer; and forming a conductive layer by alloying the first and second aluminum layers and the magnesium layer by annealing at a temperature of .
以下、第１図〜第４図により、本発明の実施例とその場
合に得られる特性とを説明する。第１図ｆａｌ 、 ｆ
ｂ）、 ｌｃｌはそれぞれ実施例構成の断面図を示して
いる。第１図において、１はＳｉ基板、２は絶縁層、３
はＭｇ堆積膜、４はＡｅ堆積膜、５はコンタクトホール
、６はＭとＭｇとの合金薄膜を示す。Examples of the present invention and characteristics obtained therein will be described below with reference to FIGS. 1 to 4. Figure 1 fal, f
b) and lcl each show a cross-sectional view of the configuration of the embodiment. In FIG. 1, 1 is a Si substrate, 2 is an insulating layer, and 3 is a silicon substrate.
4 is an Mg deposited film, 4 is an Ae deposited film, 5 is a contact hole, and 6 is an alloy thin film of M and Mg.
第１の実施例構成である第１図ｔａ＋においては、Ｍｇ
堆積膜３が、絶縁層２にあけられたコンタクトホール５
に充填され、かつ、絶縁層２の上面を覆うように形成さ
れ、このＭｇ堆積膜３を覆って、より厚いＭ堆積膜４が
形成され、２層構造の導電性層となっている。フンタク
トホール５に充填されたＭｇ堆積膜３の下面は、直接、
下地のＳ１基板面と接触している。Ｍｇ堆積膜３及びＭ
堆積膜４は電子ビーム装置を用いて形成することができ
る。In FIG. 1 ta+, which is the configuration of the first embodiment, Mg
The deposited film 3 forms a contact hole 5 formed in the insulating layer 2.
A thicker M deposited film 4 is formed to cover the Mg deposited film 3, forming a two-layer conductive layer. The bottom surface of the Mg deposited film 3 filled in the empty hole 5 is directly
It is in contact with the underlying S1 substrate surface. Mg deposited film 3 and M
The deposited film 4 can be formed using an electron beam device.
第３図の関係曲線は、第１図ｉａ）に示したＭｇ及びＭ
の堆積膜を４探剣法にて抵抗率ρ（／ｌΩ・ｃｍ）を測
定した結果を示したものである。試料としては、Ｍｇ堆
積膜３とＡｌ堆積膜４との全体の厚さを１μｍ一定とし
、Ｍｇ堆積膜３の厚さｔＭｇを変化させて抵抗率を求め
た。第３図より、Ｍｇ堆積膜の厚さｔＭｇが０３μｍの
場合においても、抵抗率ρとしては純Ａｌ膜の場合に比
べて１０％程度の増加に留っており、ＴｉやＭｏ等に比
べて格段に小さな値であることが判る。The relationship curve in Figure 3 corresponds to the Mg and Mg shown in Figure 1 ia).
This figure shows the results of measuring the resistivity ρ (/lΩ·cm) of the deposited film using the four-probe method. As a sample, the total thickness of the Mg deposited film 3 and the Al deposited film 4 was kept constant at 1 μm, and the resistivity was determined by varying the thickness tMg of the Mg deposited film 3. From Figure 3, even when the thickness tMg of the Mg deposited film is 0.3 μm, the resistivity ρ only increases by about 10% compared to the case of pure Al film, and compared to Ti, Mo, etc. It can be seen that this value is extremely small.
第１図（ｂｌは第２の実施例構成を示し、これは、コン
タクトホール５のＳｉ基板面に接する側にのみＭｇ堆積
膜３が形成され、このＭｇ堆積膜３の上面及び絶縁層２
の上面は全てＡＩ！堆債堆積が形成される構造であり、
絶縁層２の上面にＭｇ堆積膜を形成することによる製造
工程時の不安定さを減少させ得る効果がある。FIG. 1 (bl shows the configuration of the second embodiment, in which the Mg deposited film 3 is formed only on the side of the contact hole 5 that is in contact with the Si substrate surface, and the upper surface of this Mg deposited film 3 and the insulating layer 2
The top surface is all AI! It is a structure in which a bank deposit is formed,
Forming the Mg deposited film on the upper surface of the insulating layer 2 has the effect of reducing instability during the manufacturing process.
第１図ｔｃ］は第３の実施例構成を示し、これは、導電
性層がＡｌｌ−ＸＭｇＸの合金薄膜６より成る構造であ
る。FIG. 1tc] shows the structure of a third embodiment, in which the conductive layer is composed of an alloy thin film 6 of All-XMgX.
第２１／１は第１図（Ｃ１の合金薄膜６を形成する一実
施例を説明する断面図である。第２図において、まず、
Ｓｉ ２４！ｉ仮１の表面に絶縁層２を形成し、この絶
縁層２にコンタクトポール５を設ケる。次に、このコン
タクトホール５にのぞむ８１基板１の表面と、コンタク
トホール５の立ち上がり部（開口側端部）と、絶縁層２
の上面を覆って薄い第１のＡｌ堆積膜４′を形成する。21/1 is a sectional view illustrating an example of forming the alloy thin film 6 of FIG. 1 (C1). In FIG.
Si 24! An insulating layer 2 is formed on the surface of the i temporary 1, and a contact pole 5 is provided on this insulating layer 2. Next, the surface of the 81 substrate 1 that extends into the contact hole 5, the rising part (opening side end) of the contact hole 5, and the insulating layer 2
A thin first Al deposited film 4' is formed to cover the upper surface of the substrate.
次に、この第１のＡｌ ｔｌｌｉ積膜４′を覆ってＭｇ
堆積膜３を形成し、さらに、Ｍｇ堆積膜３を覆って第２
のＡｌ堆積膜４を形成する。Next, Mg is applied to cover this first Al tlli stack 4'.
A deposited film 3 is formed, and a second deposited film 3 is formed covering the Mg deposited film 3.
An Al deposited film 4 is formed.
次いで、所定の温度でアニールして上記第１のＭ堆積膜
４′、Ｍｇ＃１積膜３、第２のＡｌ堆積膜４を合金化し
て、第１図（Ｃ）に示す合金薄１摸６を形成する。Next, the first M deposited film 4', the Mg#1 deposited film 3, and the second Al deposited film 4 are alloyed by annealing at a predetermined temperature to form the alloy thin film 1 shown in FIG. 1(C). form 6.
なお、上記実施例製造方法は、堆ｖｉ膜を３層構造に形
成しておいてアニールするとしたが、これは必らずしも
３層構造とする必要はな（，２ｆ−構造Ｉこ形成してか
らアニールする方法でも合金薄膜６を形成することは可
能であり、また、スパッタリング装置により形成するこ
とも可能である。スパッタリンク装置による時は、Ａｌ
トｘ Ｍ ｇｘの合金組成比Ｘは、ターゲットのＡｔ
とＭｇの割合によって決定される。In addition, in the manufacturing method of the above embodiment, the deposited VI film is formed into a three-layer structure and then annealed, but this does not necessarily have to be a three-layer structure. It is possible to form the alloy thin film 6 by a method in which Al
The alloy composition ratio X of the target At
and the ratio of Mg.
第４図に示す関係曲線は、矩形の平面形状を持つフンタ
クトホールにおいて、同じＳｉ基板を用いて純Ａ／とＭ
ｇ −Ａ／合金薄膜をそれぞれ堆積し、コンタクト長ｄ
（第１図及び第２図断面図におけるコンタクトホール５
の図面左右方向での寸法）を１〜１０μｍの範囲で変化
させ、コンタクト幅Ｗ（第１図及び第２図断面図におけ
るコンタクトホール５の図面表裏方向での寸法）を３４
μｍ一定とした場合の、コンタクト抵抗ＲＣＯのコンタ
クト長ｄ依存性を比較したものである。Ｓｉ基板にはＰ
型、抵抗率ρが４０〜６０Ω・印のものを用い、これに
コンタクトホールを含むアイランド部にＰｈｏｓｐｈｏ
ｒｕｓを１００に■、４Ｘ１０１６／／ｃｍ−２の条件
でイオン注入し、１０００ｃ。The relationship curve shown in Fig. 4 shows that pure A/ and M
g-A/alloy thin film is deposited, and the contact length d
(Contact hole 5 in the cross-sectional views of Figures 1 and 2)
The contact width W (the dimension in the front and back directions of the contact hole 5 in the cross-sectional views of FIGS. 1 and 2) was changed from 1 to 10 μm.
This is a comparison of the dependence of contact resistance RCO on contact length d when μm is constant. P on the Si substrate
A mold with a resistivity ρ of 40 to 60 Ω is used, and Phospho is used in the island portion including the contact hole.
rus to 100, ion implantation was performed under the conditions of 4X1016//cm-2, and 1000c.
１時間のアニールを行なった。配線形成には、リフトオ
フ工程を用い、電子ビーム装置により、純Ａｔ？の場合
もＭｇ−Ａ／合金薄１模の場合も全体（漢厚を１μｍと
した。Ｍｇ−Ａｅ８合金薄膜おいては、それぞれの堆積
厚さがｔＭ、 ＝ｏ、３ ｐ ｍ ＋ ｔＡｌ−０−７
ｐ ｍ＆ ２層＋ｆｌｉ造に形成してから２３０℃のン
／タリングを行なった。Annealing was performed for 1 hour. For wiring formation, a lift-off process is used and an electron beam device is used to form pure At? In the case of Mg-A/alloy thin 1 model, the total thickness is 1 μm.In the case of Mg-Ae8 alloy thin film, each deposited thickness is tM, = o, 3 p m + tAl-0 -7
After forming a p m & 2 layer + fli structure, it was subjected to printing/taring at 230°C.
第４図を見て明らかなように、Ｍｇ−Ａｌ合金薄膜はｄ
）５．７ｚｍにおいて純Ｍの場合に比べてコンタクト抵
抗値ＲＣＯは％以下と小さく、電１ん集中を考ｉＷ Ｌ
だ分布定数解法により求めた以下の（１）〜（３）式。As is clear from Figure 4, the Mg-Al alloy thin film is d
) At 5.7zm, the contact resistance value RCO is as small as % or less compared to the case of pure M, and considering the concentration of current iW L
The following equations (1) to (3) were obtained using the distributed constant solution method.
Ｒｃ（、＝＝Ｚｏ−ｃｏｔｈけ、 ｄ ） ・
・−・＝ ｍγ−（「ｚば ・・・・・・・・
（３）より、面積換算のコンタクト抵抗ρ。は、第４図
の実測値を代入して。Rc(,==Zo-cothke, d) ・
・−・= mγ−(``zba ・・・・・・・・・
From (3), the contact resistance ρ in terms of area. By substituting the measured values in Fig. 4.
Ａｌの場合 ρ。、、 ＝ ２ Ｘ １０−６Ω・ｄ
Ｍｇ Ａｌの場合ρ。ｌｉｌｇ−Ａｚ：：２．５ Ｘ
１０−７Ω・ｄとなり、Ｍに比べＭｇ−Ａｌ合金薄膜
の方が約１桁小さくなり、１０−７Ω・４台の値を得る
ことができる。In case of Al, ρ. ,, = 2 x 10-6Ω・d
For MgAl, ρ. lilg-Az::2.5X
The resistance value of the Mg-Al alloy thin film is about one order of magnitude smaller than that of M, and a value in the order of 10-7Ω·4 can be obtained.
なお、（２Ｌ （３１式中のＲ８はコンタクト面のノー
ト抵抗である。Note that (2L (R8 in formula 31 is the note resistance of the contact surface).
以上説明したように、半導体装置にｌＶｉｇとＡｔの両
者を含む配線金属を用いることは、配線金属としての必
須条件である低コ／タクト抵抗、低抵抗率の条件を十分
満足するものであり、従来のＡＩ！を単独に用いる場合
に比べ、抵抗率はほぼ同等で、コンタクト抵抗を１桁程
度小さくすることが可能となり、微細化配線、多層配線
等において有用である。As explained above, using a wiring metal containing both lVig and At in a semiconductor device satisfies the requirements of low co/tact resistance and low resistivity, which are essential conditions for a wiring metal. Conventional AI! The resistivity is almost the same and the contact resistance can be reduced by about an order of magnitude compared to the case of using only one of the two, making it useful for miniaturized wiring, multilayer wiring, etc.
第１図は本発明の実施例図で（ａ）はＭｇとＡｊ’の２
重溝造の、＋ｂ）はＭｇをコンタクトホール中へ埋込む
ｉｉａ造の、ｉｃｌ Ｉｔ Ｍｇ−Ａｔ合金膜構造の断
面図、第膜厚依存性を示す曲線図、第４図は純ＡＩ！及
びＭｇ−ＡＪ金合金コンタクト抵抗の比較曲線図、第５
１ｚ１は従来の配線金属の抵抗率とコンタクト抵抗との
関連説明図である。
く符号の説明〉
ｌ・・・Ｓｉ基板
２・・絶縁層
３・・Ｍｇ堆積膜
４ 、４’−ＡＩ！Ｉｔ膜
５・・コンタクトホールFig. 1 is an embodiment of the present invention, and (a) shows the 2 of Mg and Aj'.
+b) is a cross-sectional view of the ICL It Mg-At alloy film structure of IIA construction, in which Mg is buried in the contact hole, and a curve diagram showing the dependence on film thickness. Figure 4 is pure AI! and Mg-AJ gold alloy contact resistance comparison curve diagram, No. 5
1z1 is an explanatory diagram of the relationship between the resistivity of a conventional wiring metal and the contact resistance. Explanation of symbols> l...Si substrate 2...Insulating layer 3...Mg deposited film 4, 4'-AI! It film 5...contact hole
Claims (5)
口部を有し、この開口部を介して上記半導体基板の内部
領域と電気的に連接すべく、上記絶縁層の上面及び上記
開口部に形成される導電性層を有する半導体装置におい
て、導電性層がアルミニウムとマグネシウムを含むこと
を特徴とする半導体装置。(1) An insulating layer is provided on the surface of the semiconductor substrate, an opening is provided in the insulating layer, and the upper surface of the insulating layer and the A semiconductor device having a conductive layer formed in an opening, the conductive layer containing aluminum and magnesium.
絶縁層の上面に形成された薄いマグネシウム膜と、この
マグネシウム膜を覆って形成された厚いアルミニウム膜
との２層構造から成ることを特徴とする特許請求の範囲
第１項記載の半導体装置。(2) The conductive layer has a two-layer structure including a thin magnesium film filled in the opening and formed on the upper surface of the insulating layer, and a thick aluminum film formed to cover this magnesium film. A semiconductor device according to claim 1, characterized in that:
接する側にのみ形成された薄いマグネシウム膜と、この
マグネシウム膜の上面及び前記絶縁層の上面を覆って形
成された厚いアルミニウム膜とから成ることを特徴とす
る特許請求の範囲第１項記載の半導体装置。(3) The conductive layer includes a thin magnesium film formed only on the side of the opening in contact with the semiconductor substrate surface, and a thick aluminum film formed covering the upper surface of the magnesium film and the upper surface of the insulating layer. A semiconductor device according to claim 1, characterized in that the semiconductor device comprises:
の合金から成ることを特徴とする特許請求の範囲第１項
記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the conductive layer is made of an alloy of magnesium and aluminum.
絶縁層の所定の位置に開口部を設ける工程と、この開口
部にのぞむ上記半導体基板表面と、上記絶縁層の上面及
び開口側端部を覆って薄い第１のアルミニウム層を形成
する工程と、この第１のアルミニウム層を覆ってマグネ
シウム層を形成する工程と、このマグネシウム層を覆っ
て第２のアルミニウム層を形成する工程と、次に所定の
温度でアニールすることにより上記第１のアルミニウム
層と上記マグネシウム層と上記第２のアルミニウム層と
を合金化させてアルミニウムとマグネシウムの合金から
なる導電性層を形成する工程とを含むことを特徴とする
半導体装置の製造方法。(5) a step of forming an insulating layer on the surface of the semiconductor substrate; a step of providing an opening at a predetermined position in the insulating layer; and a step of forming an opening on the surface of the semiconductor substrate looking into the opening, an upper surface of the insulating layer, and an end on the side of the opening. forming a thin first aluminum layer over the first aluminum layer; forming a magnesium layer over the first aluminum layer; forming a second aluminum layer over the magnesium layer; Next, by annealing at a predetermined temperature, the first aluminum layer, the magnesium layer, and the second aluminum layer are alloyed to form a conductive layer made of an alloy of aluminum and magnesium. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20802484A JPS6187366A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20802484A JPS6187366A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6187366A true JPS6187366A (en) | 1986-05-02 |
Family
ID=16549407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20802484A Pending JPS6187366A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187366A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159064A (en) * | 1988-12-13 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5117665A (en) * | 1974-08-05 | 1976-02-12 | Nippon Telegraph & Telephone | Handotaisochino seizohoho |
| JPS5252368A (en) * | 1975-10-24 | 1977-04-27 | Mitsubishi Electric Corp | Semiconductor device |
-
1984
- 1984-10-05 JP JP20802484A patent/JPS6187366A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5117665A (en) * | 1974-08-05 | 1976-02-12 | Nippon Telegraph & Telephone | Handotaisochino seizohoho |
| JPS5252368A (en) * | 1975-10-24 | 1977-04-27 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159064A (en) * | 1988-12-13 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
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