JPS6186847A - Cpu runaway preventing device for automobile controller - Google Patents

Abstract

PURPOSE:To monitor the runaway of plural CPUs with just a single runaway monitor circuit by supplying the program run signal of a CPU at one side to a CPU at another side and then supplying the program run signal of the CPU at the other side to the program runaway monitor circuit. CONSTITUTION:The 2nd CPU13 decides whether the 1st program run signal (P-RUN)A given from the 2nd CPU12 is normal or not. When the signal (P-RUN)A is normal, the CPU13 produces the 2nd P-RUN signal B. However the signal B is stopped if the cPU13 has a fault and executes no program. Thus a CPU runaway monitor circuit 14 delivers a fault detecting signal C. the 2nd P-RUN signal B is not produced regardless of a normal or abnormal state of the CPU13 as long as the signal A is not normal. Therefore, both CPU12 and 13 are reset by the signal C in case either one of CPU12 and 13 has a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a CPU runaway prevention device in an automobile control device using a plurality of CPUs.

<Prior Art> For example, since microcomputers have been used to control automobile engines, there has been a strong demand for the consolidation and sophistication of many functions. As a countermeasure against this problem, a method has been proposed in which multiple CPUs are provided and the functions are shared, thereby simplifying the control of each cPU, improving efficiency, and shortening the execution time (Japanese Patent Application Laid-Open No. 59-1999). -108847).

By the way, such automobile control devices are usually provided with a device to prevent the CPU from running out of control as a safety measure.
Conventionally, a runaway monitoring circuit 3.4 is usually provided for each CPU 1.2 in the control unit 5, as shown in FIG. That is, a program run signal (hereinafter referred to as 1" RUN signal) is output from the output port of each CPU 1.2 to each corresponding monitoring circuit 3, 4, and each P'-R
Depending on the presence or absence of the UN signal, each monitoring circuit 3.4 detects an abnormality in the corresponding CPUI, 2, and when an abnormality occurs, the CPUI
, 2 to output a reset signal.

<Problems to be Solved by the Invention> However, the conventional configuration in which a runaway monitoring circuit is provided for each CPU is disadvantageous in terms of cost and mounting space.

The present invention was made with the aim of solving the above problems, and a single CPU runaway monitoring circuit can control multiple CPUs.
This is to prevent runaway behavior.

Means for Solving the Problems〉 Therefore, in the present invention, as shown in FIG.
The first P-RUN signal output from the other CPU is input to the other CPU, and the second P-RUN signal output from the other CPU is input to a single CPU runaway monitoring circuit. A determining means for determining whether the 1P-RUN signal is abnormal or normal is provided, and a stopping means for stopping the generation of the 2nd P-RUN signal when the determining means determines that the 1P-RUN signal is abnormal, and a reset signal for the runaway monitoring circuit is provided. CPU
It was configured to output to .

This causes one CPU to be in an abnormal state and its P-
When the RUN signal (first P-RUN signal) is abnormal or when the other CPU itself is in an abnormal state, the P'-RUN signal (second P-RUN signal) of the other CPU is sent to the CPU runaway monitoring circuit.
N signal) is not input, and each CPU is reset by a single CPU runaway monitoring circuit.

<Example> Embodiments of the present invention will be described below based on the drawings.

FIG. 2 shows an example of the hardware configuration of the present invention.

In the figure, the control unit 11 has two first
and a second CPU U12.13.

As in the prior art, each of the CPUs 12 and 13 has a function of performing control assigned to each CPU according to its own control processing program.

In this embodiment, the input port of the first P-RUN signal signal box 2CPU 13 outputted from the output port of the first CPU 12 is manually inputted, and the CPU runaway of the second P-RUN signal signal outputted from the output port of the second CPU 13 is performed. It is input to the monitoring circuit 14.

The second CPtJ13 has a first P-RtJN.
A first P-RUN signal determining means that determines whether the signal A is normal or abnormal; and a second P-RUN signal that is output by the second CPU U13 based on the signal from the determining means when the determining means determines that the signal A is abnormal.
A second P-RUN signal stopping means is provided for stopping the P-RUN signal light. Further, the CPU runaway monitoring circuit 14 includes a cpu abnormality detection circuit that detects abnormality of the CPU based on the state of the second P-RUN signal, and a RESE of each CPU 12 and 13 in response to an abnormality detection signal from the detection circuit.
A center circuit is provided for outputting a reset signal to the T terminal.

Next, the operation will be explained based on the flowchart of FIG.

This is a flowchart of the second CPU 13, and first,
Initialize with SL. Next, at 82, the first CPU1
The presence or absence of the first P-RUN signal from '2, ie, whether it is normal or abnormal, is determined. Here, if the first CPU 12 operates normally and the first P-RUN signal determination result is normal, the process advances to S3, where the second P-RUN signal is generated, and then the S
4, the control processing program assigned to the second CPU 13 is executed, but if an abnormality occurs in the second CPU 13 and the program is not executed, the second P-RUN signal is stopped. Then, the CPU abnormality detection circuit of the CPU runaway monitoring circuit 14 outputs an abnormality detection signal to the reset circuit based on this, and the reset circuit outputs the first and 20th P 012゜13.
A reset signal is input to each CPU 12゜1.
Reset 3.

On the other hand, when the first P-RUN signal is present in the determination in S2, the second P-RUN signal is activated regardless of whether the second CPU 13 is normal or abnormal.
RUN signal light is not generated. Therefore, each CP012 and CP013 is reset by a reset signal from the reset circuit.

In this way, a plurality of CPUs 12 and 13 can be monitored by one monitoring circuit 14, and the CPU
Since the control unit can be prevented from running out of control, it is possible to reduce the size and cost of the control unit.

<Effects of the Invention> As described above, according to the present invention, in an automobile control device equipped with a plurality of CPUs, the P-RU of one CPU
Input N signal to the other CPU, P-R of the other CPU
The configuration is such that the UN signal is input to a single CPU runaway monitoring circuit, and abnormalities in multiple CPUs are detected and reset based on the presence or absence of the P'-RUN signal input to the monitoring circuit. It is not necessary to provide the same number of controllers (only one controller is required, and the control unit can be made smaller and the cost can be reduced).

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a hardware configuration diagram of an embodiment of the present invention, FIG. 3 is a flowchart of the same embodiment, and FIG. 4 is a hardware configuration of a conventional example. It is a diagram. 11...Control Unino I-12...1st C
PU13...2nd CPU 14...CPU runaway monitoring circuit A...1st P-RTJN signal B...
2nd P-RUN Signal Patent Applicant Japan Electronics Co., Ltd. Agent Patent Attorney Fujio Sasashima Figure 1 Figure 2

Claims (1)

[Claims] In an automobile control device that includes multiple CPUs and has a CPU runaway monitoring circuit that detects CPU abnormalities based on program run signals from the CPUs and resets the CPUs in the event of an abnormality, the first program run output from one CPU The signal is input to the other CPU, and the second program run signal output from the other CPU is input to a single CPU runaway monitoring circuit. and a stopping means for stopping the generation of the second program run signal when the determining means determines that there is an abnormality,
A CPU of a control device for an automobile, characterized in that a reset signal of the runaway monitoring circuit is output to each CPU.
Runaway prevention device.