JPS6186834A - Transfer device for picture data - Google Patents

Abstract

PURPOSE:To omit a special exclusive memory by thinning and producing discontinuous addresses during the DMA transfer to transfer a picture to be enlarged and reduced between the 1st and 2nd picture memory means. CONSTITUTION:The number of vertical and horizontal picture elements of a picture memory 11 are defined as Y ands X; while the number of vertical and horizontal picture elements of a frame memory 16 are defined as (y) and (x) respectively. Then a picture having vertical an horizontal numbers of pictures (y') and (x') is transferred. In this case, a X=x', and b.Y=y' are satisfied. Then the picture data in the memory 11 is reduced down to 1/2 vertically and horizontally and written to a frame memory 16 (a=b=1/2, X=x' and Y=y'). In such a case, the data delivered successively from the memory 11 via a thinning circuit 14 and written to the memory 156. Then the next X pieces data are all thinned and not written to the memory 16 after the first X piece of data are received. The number of addresses is increased one by one when addresses are produced from a DMAC17, and (x-x') is added to the address.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an image data transfer device.

(Prior art) For example, when an image stored in an image memory is enlarged or reduced and displayed on a display, it is necessary to transfer image data between the display frame memory and the image memory. As an image data transfer device, there is a conventional image data transfer device having the configuration shown in No. 2 [4]. This image data transfer device includes a memory 4 located at a different address from the image memory 1 and the frame memory 8 of the display 2.
, and when enlarging or reducing the image stored in the image memo IJ 1 and writing it to the frame memory 8,
First, addresses are continuously generated from the direct memory access controller (DMAO) 5 to the image memory 1 and memory 4, and the image data stored in the image memory 1 is transferred and written to the memory by DMA, and then the processor 6 generates discontinuous frame memory addresses for the frame memory 8, and in the case of reduction, thins out the image data sequentially output from the memory 4, and converts the image data from the memory 4 into frames. By transferring the image to the memory 8, the image is enlarged or reduced. In addition, when enlarging or reducing the image in the frame memory δ and transferring 1 or a part of the image in the frame memory 3 to the image memory, the image data in the frame memory 8 is similarly processed by the processor 6 in a discontinuous manner. The image data is accessed and written to the memory 4, and then the image data in the memory 4 is transferred to the image memory 1 using DMA05.

However, in such conventional image data transfer devices,
Since memory 4 is required in addition to frame memory 3,
The structure becomes complicated and expensive, and since the image data is transferred between the image memory 1 and the frame memory 8 via the memory 4, there are problems in that the transfer time is long.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide an image data transfer device that is simple and inexpensive, and that is appropriately configured to transfer required image data in a short time. It is.

(Summary of the Invention) An image data transfer device of the present invention is provided between a first image storage means and a second image storage means, and generates discontinuous addresses for the second image storage means. Then, under the control of the discontinuous addresses, the image data from the first image storage means is directly stored in a predetermined storage position of the second image storage means, and the second image storage means The apparatus is characterized in that it includes a transfer control means for reading out image data from the image storage apparatus and directly transferring the image data to the first image storage means.

(Embodiment) FIG. 1 shows a circuit configuration of an example of an image data transfer device of the present invention. In this example, an image memory 11 of an image data recording device for recording and reproducing image data is connected to a frame memory 16 of a display 15 via an interface 12.18 and a thinning circuit 14, and the frame memory 16 is connected to a discontinuous address. The image data is directly transferred between the image memory 11 and the frame memory 16 through the thinning circuit 14 under the control of the DMA 017 which has a function of generating the image data. In addition, in FIG. 1, numerals 18 and 19 indicate data lines, and 20 indicates I/F.
21 represents a memory control line, and 22 represents an address line.

Here, as shown in FIG. 8, the number of horizontal pixels of the image memory 11 is X1, the number of vertical pixels is Y, the number of horizontal pixels of the frame memory 16 is XS, the number of vertical pixels is y, and the number of horizontal pixels is When transferring the image 24 whose number is y' and the number of vertical pixels is y', the relationship is a - x - x', b - Y - y' (a and b are integers of 1 or more or reciprocals of integers). If this holds true, by appropriately setting the rules for thinning image data in the thinning circuit 14 and the rules for generating addresses from DMA017, any X + Y t X* 'j
(7) Image data can be transferred. - For example, a-b-%, X
When transferring image data from the image memory 11 to the 7-frame memory 16 as -x', Y-y, the first frame circuit 14 thins out the data sequentially output from the image memory 11 every other frame. When data is written to the memory 16 and the thinning circuit 14 receives X pieces of data, the next X pieces of data are all thinned out so as not to be written to the frame memory 16, and the address generation from DMA017 increments the address by 1. It is only necessary to add (x - x') to the address only when X/Iil is counted. This allows the image data in the image memory 11 to be
It can be written into the frame memory 16 after being reduced in horizontal %.

FIG. 4 shows the decimation circuit 14 and DMA shown in FIG.
This figure shows a circuit configuration in which 017 is realized by microprogram control. Various programs are stored in the microprogram memory 31, and a corresponding program is selected by inputting a mode select signal to an upper address of the program from a keyboard (not shown) or the like via the CPU. In this program, if the number of bits of the mode select signal is m, two can be selected. For example, as shown in FIG. 5, from the most significant bit to the least significant bit, the program module includes a controller instruction hood 82, controller data 33, adder/counter data 84, an acknowledgment signal (ACK) a5, and an address clock. 38, counter clock 37, input load signal 38, frame memory 16 (see Figure 1)
Memory write signal a9 that controls writing and reading of
and memory read signal 40, and the flow of the program is controlled by giving an address from the microprogram controller 41 to the microprogram memory 31 based on the instruction code signal for the controller. ing.

Note that the microprogram controller 41 includes a CP
A program execution clock and a request signal (REQ) indicating a condition input in a conditional jump are input from U, and data such as a counter used in the controller 41 and a jump destination address are obtained from the controller data signal of the selected program. Given.

The output of the microprogram memory 81 is the D7 rib 70.
Latched in the knob 42, in synchronization with the program execution clock, the instruction code signal for the controller and the data signal for the controller are sent to the microprogram controller 41, the data signal for the adder/counter is sent to the adder 48 and the down counter 44, and the AOK is sent to the microprogram controller 41. To the CPU (not shown), an address clock is applied to an A N D gate 45, a counter clock and a counter load signal are applied to a down counter 44, and a memory write signal and a memory read signal are applied to a buffer 46.

The down counter 44 counts the number of pixels of an image, and loads an adder/counter data signal using a counter load signal and counts down the adder/counter data signal using a counter clock. The buffer 4 outputs an RC signal to the D7 lip 70 knob 47 in synchronization with the end of data transfer, and outputs the addresses of the buffer 46 and frame memory 16.
8 is disabled, thereby setting the memory write signal, memory read signal, and address signal to high impedance to prevent m-image data from being transferred.

On the other hand, the start address data from the CPU is similarly
Buffer 4 is set by the set start address from PU.
9 to the D7 rib 70 rib 50, thereby setting the first address of the DMA address. The output of this D7 lip flop 50 is the frame memory 16.
It is output as the address of D7 through the buffer eye 8, and is added to the adder/counter data signal in the adder 48, and then sent to the D7 rib 70 through the buffer 51.
0 input and is set by the address clock via AND gate 45.

That is, the data to be added to the adder/counter data signal is output from the D7 rib 70 and the address clock is used to add the address of the frame register 16 by the amount of the adder/counter data signal. Note that the buffer 51 is provided to prevent severe data collision when writing the start address to the D flip-flop 50.

In this example, the image memory 11 is
It inputs and outputs data to and from image memory 1.
70-chart of the data output operation from the image memory 11 when transferring image data from the frame memory 16 to the frame memory 16 is shown in FIG. 70-charts of the data input operations at 11 are shown in FIG. 6B, respectively.

, An example of a microprogram will be described below.

FIG. 7 shows a 70-chart of a microprogram for reducing and writing an image stored in the image memory 11 into the frame memory 16. In this case,
First, the number of pixels (xl·y') of the image to be reduced and written into the frame memory 16 is set in the down counter 44. This counter setting operation is performed according to the flowchart shown in FIG. Next, the count value of the horizontal pixel number i of the image to be written in the frame memory 16 is set to an initial value, and the initial address N is outputted to write data to the corresponding address in the frame memory 16. This memory write operation is performed according to the flowchart shown in FIG. After writing the memory, the horizontal pixel number i is incremented, and the count value of the first pixel hj is set to the initial value, and the first reading is j − (1/a −1) while returning ACK according to the flowchart shown in FIG. ) times. However, a indicates the horizontal reduction ratio of the image. Then change the address N to l/a
The above operation is repeated until i-y' is reached.

, As a result, when the image data of the number of pixels X in one row of the image memory 11 is a-%, it is thinned out every other pixel, and when it is a-%, the second of the eight sequential pixels S8 The th pixel is thinned out, and data of aX-x' pixels is written in a predetermined row of the frame memory 16. Next, 7
In order to write to the next line of frame memory 16,
Add (x - x') to address N, perform the address counting operation according to the flowchart shown in Figure 11, then set the count value for the number of reading pixels to the initial value, and then read as shown in Figure 10. The process is carried out -X·(1/b -1) times (b is the reduction ratio in the vertical direction of the image) according to the flowchart shown. However, X represents the number of pixels in one row of the frame memory 16. As a result, when b-%, all the image data in the second row of the image memory 11 is thinned out, and when b
- In this case, all the image data in the second and eighth rows will be thinned out.

By repeating the above operations, the image memory 11
The image stored in the image memory 11 is directly transferred from the image memory 11 to the frame memory 16 and written therein, with the image multiplied by a in width and multiplied in height.

FIG. 12 shows that in the above microprogram control, a
-b- shows a time chart when the image memory 11. The image 55 stored in the 7-frame memory 16 is written into the 7-frame memory 16 as an image 56 reduced in vertical and horizontal % by thinning.

FIG. 14 shows the microprogram 70→yard when an image stored in the image memory 11 is enlarged and written to a 7-frame memo I716. In this case, first, by the counter setting operation shown in FIG. 8, the number of pixels (x'
-y') is set in the down counter 44. next,
The counted value of the number of pixels in one line of the image to be written to the frame memory 16, the number of pixels written in the horizontal direction of the same data according to the horizontal enlargement magnification ia of the image, and the height of the same data according to the vertical enlargement magnification of the image In addition to setting each count value for the number of writing pixels in the direction to the initial value, the initial address N is output and the memory line (70- without AOK) shown in FIG. 15 is set.
Data is written into the frame memory 16 according to the chart. This operation is performed while increasing the address N by X until it becomes -b. However, no ACK is returned. As a result, the data of one pixel in the image memory 11 is written into sequential b pixels of the 7-frame memory 16 in the vertical direction.

Next, the address N is decreased by (bx-1) to access the pixel next to the first written pixel, and the address is counted according to the address counting operation shown in FIG. Increment the number of pixels j and the number i of pixels in one line of the image.

After repeating the above operation until the number k of pixels in the vertical direction of the same data reaches ja without resetting it, an ACK IJ turn is performed according to the 70-chart shown in FIG. As a result, data for one pixel in the image memory 11 is written to axb adjacent pixels in the frame memory 16. After performing the above operations until the end of the line, address N
Add (x-x') +x(b-1) to the address count shown in FIG. Then, write the row after row b in the same way.

By repeating the above operations, the image memory 11
The image stored in the image memory 11 is directly transferred from the image memory 11 to the frame memory 16 and written therein, with the image multiplied by 8 times horizontally and vertically.

Figure 17 shows that in the above microprogram control a=
b-19, and as shown in FIG. 18, the framed memory 16 stores an image 58 which is twice the vertical and horizontal magnification of the image 57 stored in the image memory 11. is written. Note that four vertically and horizontally adjacent pixels shown enlarged in FIG. 18 indicate the order of access when writing data for one pixel in the image memory 11.

, FIG. 19 shows a flowchart of a microprogram when an image written in the frame memory 16 is reduced and transferred to the image memory 11. In this case, first, the number of pixels (xy) of the image to be reduced and written to the image memory 11 is set in the down counter 44 by the counter setting operation shown in FIG. Next, image memory 1
Set the count value of the pixel microbeam next to the image to be written in 1 to the initial value, and output the initial address N to read the data at the corresponding address in the frame memory 16. 1, AOK
return it. This memory read operation is performed when the number of pixels i of persimmon is i=X
This is done while increasing address N by a until .

However, a represents the reciprocal of the horizontal reduction ratio of the image. As a result, one row of image data ★ in the frame memory 16 is thinned out every a and read out. Note that this memory read operation is performed according to the flowchart shown in FIG. Thereafter, (x-x')+x(b-1) is added to address N and the next row is accessed. However, b represents the reciprocal of the vertical reduction rate of the image. As a result, b=2, so when the reduction rate is %, all the image data in the second line of the frame memory 16 is thinned out, and when b=3 (reduction rate 3A), the image data in the second line All of the image data in the 8th row will be thinned out.

By repeating the above operations, the horizontal size of the image stored in the frame memory 16 is 1/a times larger.

The image multiplied by 1/b is directly transferred from the frame memory 16 to the image memory 11.

FIG. 22 shows that in the above microprogram control, a
This shows a time chart when =b=2, and as shown in Fig. 23, the image 59 marked 1@ in the 7 frame memo IJ 16 is reduced vertically to the @ station as an image 60 by thinning. The image is written into the image memory 11.

In the microprogram control of this embodiment, memory write is read from, and memory read is performed as shown in FIGS. 9 and 10.
As is clear from FIGS. 15 and 21, 1. REQ
This is done after waiting until the level reaches 9L level. In addition, although variables such as i, j, and so on are used in Figures 7, 14, and 19, these are used to describe the flow of the program, and in the actual program, they are not necessarily ffu. It does not necessarily mean that it will be used.

In this embodiment, data thinning and address generation are performed under microprogram control.
By preparing a plurality of programs in the microprogram memory 31 with the same hardware configuration, it is possible to transfer various image data accompanied by enlargement and reduction operations.

Furthermore, even when changing the number of vertical and horizontal pixels in the image memory 11 and frame memory 16, this can be done simply by changing the program without changing the hardware.

(Effects of the Invention) As described above, according to the invention, image transfer involving enlargement and reduction operations between the first image storage means and the second image storage means, and partial image can be directly transferred without using a separate memory by thinning out data and generating discontinuous addresses during DMA transfer. Therefore, the configuration is simple and inexpensive, and required image data can be transferred in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an example of the image data transfer device of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional image data transfer device, and FIG. 8 is the image memory and frame shown in FIG. 1. FIG. 4 is a block diagram showing the configuration of main parts of another example of the image data transfer device of the present invention; FIG. 6A and B are flowcharts showing the data output and input operations in the image memory in FIG. 4; FIG. 7 is a diagram showing the bit allocation of the microprogram memory in FIG. A flowchart of the micro program program in the case of transfer. FIGS. 8, 9, 10, and 11 are 70-charts of the subroutine of the microprogram shown in FIG. 7. FIG. A time chart of the signal when a=b=%, FIG. 18 is a diagram showing the transfer result, FIG. 14 is a flowchart of the microprogram when enlarging and transferring from the image memory to the frame memory in FIG. 4, and FIG. 15 16 is a 70-chart of the subroutine, FIG. 17 is a time chart of the signal when a=b=2 in FIG. 14, the 18th threshold is a diagram showing the transfer result, and FIG. 19 is the Figure 4 shows the 70-chart of the microprogram when reducing and transferring from the frame memory to the image memory, Figures 20 and 21 show the 70-chart of the subroutine, and Figure 22 shows the 70-chart of the microprogram for a = b = 2 in Figure 19. FIG. 23 is a diagram showing the transfer results. 11... Image memory 12.18... Interface 14... Thinning circuit 15... Display 16... Frame memory 17... DM
A (331...Microprogram memory 41...Microprogram controller 42.47
．． 50...D flip-flop 43...Adder 44...Down counter 45...AND gate 46.48, 49.51...Buffer Figure 3 Figure 5" Figure 6 A B 12 Figure 13 Figure 20 Figure 21 Figure 22 Figure 23 Procedure Amendment Written June 10, 1985 Manabu Shiga, Commissioner of the Patent Office 1, Indication of Case Patent Application No. 206978, 1988 2, Name of the invention Image data transfer device 3 Relationship to the person making the amendment Patent applicant (037) Olympus Optical Industry Co., Ltd. 4 Name of agent (5925) Patent attorney Akihide Sugimura Address Same office Name (7205) Patent attorney Written by Oki Sugimura 5/Supplementary fJ
) v.i. Detailed Description of the Invention. Column 1, "from the CPU" on page 8, line 8 of the specification is deleted, and rCPUJ on line 17 of the same page is corrected to "interface circuit." 2. Correct "Address N" in line 11 of page 11 to "address" and change "Number of horizontal pixels 1 after memory write" in line 14 of the same page to "
After writing the memory, the address is increased by 1/a and the number of horizontal pixels is corrected to 1, and the line 19-20 of the same page is deleted, ``While the address N is increased by 1/a.'' 3, page 12, line 7, page 14, line 1, @ line 4. Line 8, line 20, page 16, line 9, line 12 and M
Correct "Address NJ" in line 2S to "Address".

Claims (1)

[Scope of Claims] 1. Provided between a first image storage means and a second image storage means, generating discontinuous addresses for the second image storage means, and generating discontinuous addresses for the second image storage means, directly storing the image data from the first image storage means in a predetermined storage location of the second image storage means under the control of a specific address, and reading the image data from the second image storage means. An image data transfer device comprising transfer control means for directly transferring data to the first image storage means. 2. The transfer control means includes a thinning means for thinning out the image data sequentially output from the first image storage means according to a predetermined rule, and a thinning means for thinning out the image data sequentially output from the first image storage means, and a discontinuous address for the second image storage means according to a predetermined rule. 2. The image data transfer apparatus according to claim 1, further comprising address generation means for generating an address. 3. The image data transfer apparatus according to claim 2, wherein the thinning means and the address generating means are configured to be controlled by a microprogram.