JPS6185165U - - Google Patents
Info
- Publication number
- JPS6185165U JPS6185165U JP16940684U JP16940684U JPS6185165U JP S6185165 U JPS6185165 U JP S6185165U JP 16940684 U JP16940684 U JP 16940684U JP 16940684 U JP16940684 U JP 16940684U JP S6185165 U JPS6185165 U JP S6185165U
- Authority
- JP
- Japan
- Prior art keywords
- conversion circuit
- level conversion
- semiconductor elements
- levels
- interconnected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例を示す上面図、第
２図は従来の半導体装置を示す図で、第２図ａは
上面図、第２図ｂは側面断面図である。 １，１ａ，１ｂ…半導体素子、２…シリコンチ
ツプ、７…レベル変換回路。なお、図中同一符号
は同一または相当部分を示す。
２図は従来の半導体装置を示す図で、第２図ａは
上面図、第２図ｂは側面断面図である。 １，１ａ，１ｂ…半導体素子、２…シリコンチ
ツプ、７…レベル変換回路。なお、図中同一符号
は同一または相当部分を示す。
Claims (1)
- 動作レベルの異なる複数の半導体素子とそのレ
ベルを変換するレベル変換回路とを同一のチツプ
上に装着し、そのレベル変換回路を介して半導体
素子間を前記チツプ上で相互接続してなる半導体
装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16940684U JPS6185165U (ja) | 1984-11-08 | 1984-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16940684U JPS6185165U (ja) | 1984-11-08 | 1984-11-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6185165U true JPS6185165U (ja) | 1986-06-04 |
Family
ID=30727145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16940684U Pending JPS6185165U (ja) | 1984-11-08 | 1984-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185165U (ja) |
-
1984
- 1984-11-08 JP JP16940684U patent/JPS6185165U/ja active Pending