JPS6185159U - - Google Patents

Info

Publication number
JPS6185159U
JPS6185159U JP16994884U JP16994884U JPS6185159U JP S6185159 U JPS6185159 U JP S6185159U JP 16994884 U JP16994884 U JP 16994884U JP 16994884 U JP16994884 U JP 16994884U JP S6185159 U JPS6185159 U JP S6185159U
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor chip
bed portion
utility
model registration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16994884U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16994884U priority Critical patent/JPS6185159U/ja
Publication of JPS6185159U publication Critical patent/JPS6185159U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051Forming additional members, e.g. dam structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP16994884U 1984-11-08 1984-11-08 Pending JPS6185159U (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16994884U JPS6185159U (de) 1984-11-08 1984-11-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16994884U JPS6185159U (de) 1984-11-08 1984-11-08

Publications (1)

Publication Number Publication Date
JPS6185159U true JPS6185159U (de) 1986-06-04

Family

ID=30727660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16994884U Pending JPS6185159U (de) 1984-11-08 1984-11-08

Country Status (1)

Country Link
JP (1) JPS6185159U (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303216A (ja) * 2005-04-21 2006-11-02 Denso Corp 樹脂封止型半導体装置
JP2010040618A (ja) * 2008-08-01 2010-02-18 Nec Electronics Corp リードフレーム、半導体装置、及び半導体装置の製造方法
JP4738983B2 (ja) * 2005-11-08 2011-08-03 ローム株式会社 半導体装置
US10546988B2 (en) 2015-08-10 2020-01-28 Panasonic Intellectual Property Management Co., Ltd. Light emitting device and solder bond structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303216A (ja) * 2005-04-21 2006-11-02 Denso Corp 樹脂封止型半導体装置
JP4609172B2 (ja) * 2005-04-21 2011-01-12 株式会社デンソー 樹脂封止型半導体装置
JP4738983B2 (ja) * 2005-11-08 2011-08-03 ローム株式会社 半導体装置
JP2010040618A (ja) * 2008-08-01 2010-02-18 Nec Electronics Corp リードフレーム、半導体装置、及び半導体装置の製造方法
US10546988B2 (en) 2015-08-10 2020-01-28 Panasonic Intellectual Property Management Co., Ltd. Light emitting device and solder bond structure

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