JPS6184704A - Sequence control circuit - Google Patents

Abstract

PURPOSE:To handle easily the abnormal processing by cascade-connecting FFs corresponding to the man-hour in a ring shape by means of interposing a delay means between FFs. CONSTITUTION:A sequence control circuit 15 is provided with RS.FFs19 corresponding to the man-hour, and a man-hour checking timer 20 is interposed as a delay means between the RS.FFs, whereby FFs19 are cascade-connected in a ring shape. Thus when an electric power source is turned on, a power-on reset signal P.ON.R is generated. The FF19 in a step 1 is set, while FFs 19 in other steps are reset through an OR gate 21. When jump conditions are not satisfied and only jogging conditions are satisfied, the man-hour checking timer 20 in the posterior stage starts its action after the setting. When the jogging conditions are satisfied after setting the set time, the FF19 in a step 2 is set, while the FF19 in the step 1 is reset. Afterwards the similar action is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The invention relates to a digitally configured sequence control circuit, and particularly problems related to interlock, timing, rotation, etc. can be easily solved 7- The present invention relates to a can control circuit.

[Background of the invention]

The concept of a stepping programmer has been around for a long time69 and has been used for control/control in which operation signals are output in a predetermined order over time. That is, when it is desired to obtain an output signal such as that shown in FIG. 4, it is not created by the entire normal sequence, but is realized by a dedicated stepping circuit that advances step 8 step by step. It is something. FIG. 5 shows an image of its configuration. Currently, many controllers of this type are commercially available, such as Freelog (
Hitachi's new product name) and step type controllers are well known.

Incidentally, to explain FIG. 5, each time there is a step input from the step input source 1, the stepping motor rotates by one pitch in the step step selector 2, and this rotation causes the rotary inch to move to the next step. When the output relay part 3 is moved by the position tiit, the relay coils 4 to 8 provided in accordance with the process are energized. In this example, the relay coil 8 needs to be excited not only in step 5 but also in step 3.4, but diodes 9 and 10 are provided to excite the relay coil 8 in steps 3 and 4, respectively. be.

By the way, it is known that this type of controller significantly reduces the number of new manufacturing steps for both design and inspection, but since it is a dedicated hardware product, the number of inputs and outputs, the number of steps,
There are limitations to the jump function, etc., and there are functional issues.
The reality is that it is not commonly used due to the drawback of increased costs. Furthermore, although the one shown in FIG. 5 has only a stepping function, if it were to be provided with a jump function, it would be as shown in FIG. 6. To explain this with reference to FIG. 7, if there is a jump input from the jump input source 12 to the jump control unit 11 no matter what step the step is in, the relay coil 13 is energized, and as a result, the break occurs. (b) Output OUT 1 to the general sequence circuit 14 via a contact.

0UT2 and 0UT4 are off, meter (a) Ia
Depending on the point, outputs 0UT3 and 0UT5 are turned on.

In this way, all jump functions must be configured outside the stepping circuit, and when many jump functions are added, the circuit configuration becomes complicated and maintenance and inspection cannot be performed easily. , causing problems. Historically, for example, when a jump input is used to jump to process 3 and then to perform a normal step operation to process 4, the process step selector needs to be devised, and it is undeniable that the circuit configuration becomes even more complex. Become something.

On the other hand, apart from this, JP-A-51-113086 discloses a sequence control circuit as a known technique, but in this case, the circuit is controlled step by step by a rotary switch. It has become.

A normal interlocking sequence consists of a circuit consisting of a step condition and an abnormality process (jump condition), but if only the step condition is set, the circuit is advanced step by step using a rotary switch. All abnormality processing requires an external circuit.

Another known technique is disclosed in Japanese Unexamined Patent Publication No. 49-27790, in which a sequence is constructed using a pin board. However, although normal interlocking sequence circuits use pinboards to increase the speed of 7-steps, abnormal processing items must be assembled externally, and there is a problem in that it is not possible to jump from one process to the previous process. .

[Purpose of the invention]

Therefore, the purpose of non-invention is to easily solve problems related to ink locks, timing, wrap-around, etc., and to easily deal with stupid or abnormal processing that can jump from one process to an earlier process. The object of the present invention is to provide a simple and easy-to-configure digitized sequence control circuit.

[Haruka of invention]

For this purpose, the present invention has a number of flip-flops (hereinafter referred to as F/F) e corresponding to the number of processes, a ring-shaped
In addition, in a cascade connection, each F/F assumes that the step condition has been titrated, and if the set output of the previous F/F is obtained from the previous JffiTD, or if there is a jump input while in the reset state. while the other F
It is designed to trigger a reset on the condition that /F is set.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 3.

First, the basic configuration of the sequence control circuit according to the invention will be explained. FIG. 1 shows the configuration assuming that the number of steps is three. As shown in the figure, the control circuit 15 is provided with an F/F 19 as an RS flip-flop corresponding to the step (STEP), and a T is connected between the F/F 19.
The F/Fs 19 are cascaded in a ring shape so that a process confirmation timer 20 as D is interposed. However, F/F at 5TEP-END
19 is essentially unnecessary, and the time-up times of the process shoe recognition timers 20 are significantly different. Although the F/F 19 is placed in a set state by a set input from the OR gate 17, it is reset by inputting a set input to another F/F 19 as a reset input via the OR gate 21. .

Now, to explain the initial settings when the power is turned on, the power-on reset signal P・ON・R is generated when the power is turned on, and while this sets the F/F 19 in process 1, It is configured to be reset by a power-on reset signal P-ONeR via an OR gate 21. The subsequent operations are different depending on whether the step condition is satisfied or the jump condition is satisfied.

First, let us explain the normal case, that is, the case where the jump condition is not adjusted and only the step condition is satisfied. By setting F/F 19 in step 1, the step memory output is obtained as the set output. However, this set output causes the process confirmation timer 20 in the immediately subsequent stage to start operating. The process confirmation timer 20 will eventually time out after the set time has elapsed, but if the step condition for process 2 is satisfied in this state, the F/F of process 2 will be activated by the OR gate 17 via the AND gate 18.
19 is set, and at the same time, the F/F 19 in step 1 is to be reset. Hereinafter, after the F/F 19 is set in step 83 in this way, the series of operations will be completed by setting the F/F 19 at the end of the process (STEP-END). Ru. Immediately after the F/F 19 at the end of the process is set, the F/F 19 at the process 1 is set, and the same operation as above is repeated again.

Next, to explain the case where the jump condition is satisfied, no matter what step the step condition is in due to satisfaction of the step condition, if the jump condition corresponding to the step is satisfied, F/F19 in that step will be changed. While it is forcibly set on the condition that it has been reset, it is forcibly reset in other processes. For example, if the jump condition corresponding to process 2 is satisfied with F/F 19 in process 2 being reset, that F/F 19 is set via the AND gate 16, and it is not used in other processes. It is reset via the OR gate 21. After this, steps are sequentially performed such as step 3, end of step, step 1, etc. unless the jump condition is satisfied. Note that the jump input for the end of a process can be considered to be for process 1. If F/F 19 at the end of the process is set by jump input, the F/F at process 1 is immediately set.
This is because F19 is set.

No matter how complex the sequence is, it can basically be replaced with a step-by-step sequence with a parent-child-one-grandchild relationship, and ice making for abnormal handling can be done in the form of an interrupt. This can be processed by jumping the process. In other words, the complexity of ink clocks, timing problems, and problems with turning around, which have always been problems when creating interlocking sequences, are solved all at once. This makes it possible to create a large amount of food, leading to a significant reduction in man-hours for both design and food inspection.

The sequence control circuit according to the present invention can basically be constructed as described above, but in the circuit shown in FIG. The number of OR gate inputs for setting /F'a-IJ is also one less than the number of steps, which is not practical.

FIG. 2 shows the configuration of a sequence control circuit designed to eliminate the above-mentioned problems.

As shown in the figure, the 71-case control circuit 22 in this example has eight steps, but the circuit operation is basically the same as that shown in FIG. However, the difference between this example and the one shown in FIG. 1 is that it is provided with an all-IJ set input terminal ARI and an all-reset output terminal AL (, O), and is configured as a basic unit. When an all-reset signal is input from the outside, the signal causes the OR gate 23 to
/F 19 is reset while or game) 24.2
1 is used to reset the F/F 19 in other processes. On the other hand, the set inputs to the F/F 19 in each process are subjected to IIX-order ORing by the OR gate 25, and then outputted to the outside as an all-reset signal. In addition, when the number of steps is 8, the output STO of the AND gate 18 in the next step STEP-NEXT is used as the power-on reset signal P・ON
-R and then apply it to the input terminal 8TI.

Now, when a predetermined number of sequence control circuits as shown in FIG. 2 are cascaded in a ring shape, sequence control in which the number of steps is a multiple of eight is generally obtained. FIG. 3 shows the configuration of a sequence control circuit with 128 steps. As shown in the figure, the sequence control circuit 26 is constructed by cascading 16 basic units, and the output 8TO from the 16th basic unit is ORed with the power-on reset signal P・0N-R by the OR gate 27. The voltage is applied to the input terminal STI in the first basic unit. In addition, the all-reset signal obtained from each basic unit can be used to reset other basic units.
The OR gate 28 outputs the logic 'A111' to be input as ta-q. Incidentally, in the sequence control circuit shown in Fig. 3, for example, the number of steps is 1.
25, the output 6 of the AND gate (18) in step 125 in the 166th basic unit may be used instead of STO.

〔Effect of the invention〕

As explained above, according to the present invention, problems related to interlocks, timing, rotation, etc. can be easily solved, and not only can it be possible to jump from the interlocking process to the previous process, but also it can be used to handle abnormalities. can be easily dealt with,
This has the effect of providing a digitized sequence control circuit with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 shows the basic h of the sequence control circuit according to the present invention.
FIG. 2 is a diagram showing the configuration of the basic unit, and FIG. 3 is a diagram showing the configuration of the basic unit.
4, 5, 6, and 7 are diagrams for explaining the conventional 7-can control circuit. 16.18...AND gate, 17.21...ORG-1, 19...Flip-flop, 2o...Process confirmation timer.

Claims (1)

[Claims] 1. A number of flip-flops corresponding to the number of processes are cascaded in a ring shape with delay means interposed between the flip-flops, and each flip-flop is connected to the previous flip-flop from the previous delay means on the premise that the step condition is satisfied. A sequence control circuit characterized in that it is set when a jump input occurs when a set output is obtained or when it is in a reset state, and is reset on the condition that another flip-flop is set.