JPS6182256A - Battery backup type storage device - Google Patents

Abstract

PURPOSE:To hold exactly data without inspecting frequently a battery by comparing a backup use battery with a reference voltage, and writing this comparing information in a specified address of a storage device. CONSTITUTION:When power is restored, a system power supply voltage VDD starts to rise, and when this voltage VDD exceeds a breakdown voltage of Zener diodes ZD1, ZD2, TRs Q1, Q3 become an on-state, by which Trs Q2, Q4 become on-state, and a chip enable signal rises to an H level. On the other hand, when a relay driver 17 is operated by a rise of the voltage VDD, a relay 16 becomes on, and a compared value of an electromotive force of a battery 14 and a voltage divided value of the voltage VDD by a comparator 15 is written on a RAM11 through a bus BUS. Accordingly, a CPU can decide whether the backup has been executed normally or not, by reading out its data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a battery backup type storage device that retains stored information using a battery when power is cut off.

[Technical background of the invention]

Conventionally, a battery backup circuit in this type of storage device is configured as shown in FIG. 5, for example.

Reference numeral 11 in FIG. 5 is a semiconductor memory device (RAM), one power supply terminal vDD of this RAM 11 is normally supplied with power from the system power supply via a power supply switching circuit 12, and the other power supply terminal vDD is normally supplied with power from the system power supply via a power supply switching circuit 12. GND is grounded. Now, R.A.
Assuming that M11 is enabled, this RAM
11 to the CPU via the system path BUS.
(not shown), or the CPU
Data is written to RAM 11 from there.

Then, when the system power supply is cut off, the RAM 11 is switched to data retention mode by the power fail signal PF of the system power supply, and data is transferred from the memory retention (backup) battery 13 to the RAM via the diode 14.
11 is supplied with power.

When the power is restored, when the voltage of the system power supply rises sufficiently, a chip enable signal is supplied from the power supply switching circuit 12 to the chip enable signal input terminal CE of the RAM 11, and the RAM II becomes enabled.

[Problems with background technology]

By the way, after the system power is restored, processing begins assuming that the data in the RAM 11 held by the backup battery 13 has not changed. However, if the electromotive force of the battery 13 decreases, part or all of the data may be destroyed, potentially causing malfunction or runaway of the entire system.

To avoid such problems, it is necessary to use a battery with a larger capacity than necessary or to frequently test the electromotive force of the battery.

[U-shaped invention]

This invention was made in view of the above circumstances,
The purpose is to provide a battery-backed storage device that can securely retain data even with a relatively small-capacity backup battery without requiring frequent inspections, and that can improve reliability.

[Summary of the invention]

That is, in order to achieve the above object, in the present invention, in a system that uses a battery to hold stored information, the electromotive force of the backup battery is compared with a predetermined reference voltage by a comparator, and the comparator By writing test information on the electromotive force of the battery to a specific address in the storage device and accessing the specific address on the system side (CPU), the validity of the held data can be confirmed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.One input terminal of a comparator 15 is connected to the positive electrode of the backup battery 13 in FIG. A connection point between resistors R1 and R2 connected in series between the system power supply and the ground point is connected to the end. The comparison output data output from the comparator 15 is stored in the RAM by connecting the relay 16 and the system path BUS.
It is written to a predetermined storage area of J1. Above relay 1
6 is controlled by a relay driver 17 to which system power is supplied.

Note that the RAM 11 is supplied with a read/write control signal R from the cPU via the system bus and the power supply switching circuit 12.

FIG. 2 shows an example of the configuration of the power supply switching circuit 12 shown in FIG. 1 above. That is, a Zener diode ZD and a resistor R3 are connected in series between the system power supply and the ground point. One end of resistor R4 is connected to the connection point between the Zener diode ZD and resistor R3, and this resistor R4
The other end is connected to the base of an NPN transistor Q1. The emitter of the transistor Q is grounded, and the collector is connected to the PNP transistor Q through a resistor R.
The pace of is connected. The system power supply is connected to the emitter of this transistor Q, and the chip enable signal CE is obtained from the collector. The above Zener diode-P
ZD'S'': L: Resistors R3 to Rs (Oyohi) Runcisors Q and +Q2 constitute a generation circuit for the chip enable signal cg. With a configuration similar to this circuit, Zener diodes ZD, resistors R6 to Rs, and transistors Q
3, Q, are connected. And the above transistor Q
The signal obtained from the collector side of resistor R91R16
and a time constant circuit 18 consisting of a capacitor C1, and this delayed output is supplied to the RAM 11 as a read/write control signal R7. The signal R output from the time constant circuit 18 is used to write inspection information for the battery 13 when the power is restored, and the signal R is supplied from the CPU via the system bus BUS during normal operation. It has become. Further, the system power is supplied to the power terminal "DD" of the RAM 11 via a diode 19.

FIG. 3 shows an example of the configuration of the relay driver 17 in FIG. 1. The coil RL of the relay 16 and the NPN transistor Q are connected between the system power supply and the ground point.
, are connected in series.

Further, a resistor R□1 is connected between the pace of the transistor Q and the system power supply, and a capacitor C3 is connected between the pace of the transistor Qi and the ground.

Next, in the above configuration, the operation at the time of power restoration will be explained using the time sequence shown in FIG. At time t0, the voltage vDD of the system power supply starts to rise, and when this voltage vDD exceeds the breakdown voltage of the Zener diodes ZD, , ZD, the transistors Ql, Q3
turns on. As a result, transistor Q2
, Q4 are turned on, and chip enable signal CE rises to a high (“H”) level at time t1. on the other hand,
Due to the rise in the system power supply voltage ■DD, time t2
When the transistor Q6 of the relay driver 17 is turned on, an exciting current flows through the coil RL of the relay 16, and the relay 16 is turned on. At this time, the electromotive force of the battery 13 and the system power source by the comparator 15 are connected to the resistors R1 and R2.
The system output data is compared with the voltage divided by
The data is written to the RAM 11 via the bus BUS.

1'1 in which the above comparison output data is written. AM 11
The address generally becomes the rOJ address or the final address when the power is restored because the address input is soled up to the power supply voltage or down to the ground side during backup. Due to the on-state of the transistor Q4, the potential of the node N rises to the 'H' level at time t3 with a time constant of (re -1-r10)c1.Here, r is the resistance value of the resistor R9, r □. is the resistance value of the resistor RIO. In Fig. 4, vDH is the data hold voltage, vTHR is the threshold voltage at the time of a read cycle, VDH' is the judgment reference voltage of the reference input, and V
RL is a voltage applied to coil RL of relay 16.

According to such a configuration, during the period between times 10 and 12,
The data obtained by testing the electromotive force of the battery 13 is stored in RAM 1.
Since this data can be written to 1, by reading this data by the CPU, it can be determined whether the pull-up has been performed normally. Therefore, system malfunctions and runaways can be prevented and reliability can be improved without using a battery with an unnecessarily large capacity or frequently inspecting the electromotive force of the battery.

In the above embodiment, the power supply switching circuit 12 does not use the HAZ4 power fail signal PF, but a configuration using this signal PF may be adopted.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a battery backup type storage device that can securely retain data even with a relatively small capacity backup battery without requiring frequent inspections, and can improve reliability.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a battery backup type storage device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the power supply switching circuit in FIG. FIG. 4 is a circuit diagram showing a configuration example of a relay driver in the circuit shown in FIG. It is. DESCRIPTION OF SYMBOLS 11...Semiconductor memory device (RAM), 12...Power switching circuit, 13...Patch IJ'-115...Comparator (comparison means), 16...Relay, 17...Relay driver .

Claims (1)

[Claims] In a system that uses a battery to retain stored information, there is a comparison means for comparing the electromotive force of the battery for storing the stored information with a predetermined reference voltage, and a comparison means that compares the electromotive force of the battery for storing the stored information with a predetermined reference voltage, and a comparison means that compares the electromotive force of the battery with a predetermined reference voltage. A battery backup type characterized in that the system CPU is configured to be able to detect a decrease in the electromotive force of the battery by referencing the test information written in the storage element. Storage device.