JP2001274666A - Reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reset circuit by which a RAM storing backup data cannot write a value of a reset signal even when a power supply voltage is lower than an operation warrant voltage of a reset IC. SOLUTION: A CR filter consisting of a capacitor 5 and a resistor 6 and provided between a supply line of a power supply voltage Vcc and a pull-up resistor 2 delays a rise in a voltage at a point B at the rising of the power supply voltage Vcc. Thus, a voltage of a reset signal inverse of RES is kept not to reach a 3rd prescribed voltage or over at which the write to the RAM is possible for a period when the rising voltage of the power supply voltage Vcc is lower than the operation warrant voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit for performing a system reset of a digital circuit of a controller of an NC machine tool or a robot.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a configuration of a reset circuit for resetting a digital circuit. This reset circuit includes a reset IC for monitoring power supply voltage such as TL7705C (manufactured by Texas Instruments).
1 is used.

The reset IC 1 monitors the value of the power supply voltage Vcc input from the SENSE terminal, and when the power is turned on, the operation guarantee voltage of the reset IC in which the value of the power supply voltage Vcc is the first predetermined value. The reset signal / RES is held at a low level (hereinafter, L) until the voltage rises from the value to the second predetermined value of 4.7 V, and the value of the power supply voltage Vcc is equal to or higher than the second predetermined value (4.7 V). / RES when
The reset signal / RES output from the ET terminal is set to L for a predetermined time T, and thereafter, the reset signal / RES is set to a high level (hereinafter, H). I for reset
C1 has a transistor inside and a reset signal / RE
S is an open collector output of the transistor, which is pulled up to the power supply voltage Vcc by the pull-up resistor 2. Capacitors 3 and 4 are inserted in parallel between the reset IC 1 and the ground. The capacitance of the capacitor 3 is 0.1 μF, and the value of the predetermined time T is determined by the capacitance Ct of the capacitor 4.

FIG. 4 is a graph showing how the reset signal / RES changes when the power supply voltage Vcc rises. When the value of the power supply voltage Vcc is equal to the second predetermined value (4.7
V) or more, the reset IC 1 turns on the internal transistor and outputs the reset signal / RES for a predetermined time T.
After that, the transistor is turned off and the reset signal / RES is set to H. The operation of the reset IC 1 is not guaranteed when the value of the input power supply voltage Vcc is lower than the operation guarantee voltage value of the reset IC 1 which is the first predetermined value. Therefore, in the rising period A in which the value of the power supply voltage Vcc is lower than the operation assurance voltage value, the value of the reset signal / RES becomes lower than the power supply voltage Vcc.
May rise with the value of. Conventionally, the reset signal / RES is used only for resetting the digital circuit, and the reset signal / RES in the period A is used.
The rise in S was not a problem.

[0005] However, when the RAM backed up by the battery is present in the digital circuit while the power is off, the data stored in the RAM is not destroyed by the instability of the signal level in the circuit when the power is turned on. As described above, the reset signal / RES may be used to deactivate the enable signal. In such a RAM, the operable voltage value is decreasing year by year. Therefore, when the value of the reset signal / RES that has risen in the period A becomes equal to or more than the third predetermined value that activates the enable signal, the RAM
However, there is a problem that data stored in the storage device may be destroyed.

[0006]

As described above, in the conventional reset circuit, when the value of the power supply voltage is lower than the operation guarantee voltage value of the reset IC at the rise of the power supply voltage, the value of the reset signal is reduced. It may increase with the value of the voltage. The value of the reset signal at that time is
When the value becomes equal to or more than a third predetermined value that enables writing to the RAM backed up by the battery,
There is a problem that data stored in the RAM may be destroyed.

According to the present invention, an IC for resetting a power supply voltage is provided.
It is an object of the present invention to provide a reset circuit that reliably holds the value of the reset signal at a value at which the RAM storing the backup data is not writable even when the voltage is lower than the operation guarantee voltage value.

[0008]

In order to solve the above-mentioned problem, the present invention is directed to a power supply voltage which is pulled up by a resistor so that the value of the power supply voltage is equal to or greater than the first predetermined value. If the value is less than a predetermined value, the power supply voltage is held at a low level, and is held at a low level for a predetermined time after the value of the power supply voltage becomes equal to or more than a second predetermined value, and then becomes a high level. In a reset circuit for outputting a reset signal, the reset circuit is provided between the power supply voltage supply line and the resistor, and when the power supply voltage value is lower than a first predetermined value, the reset signal value Is maintained at a value lower than a third predetermined value.

According to the present invention, the voltage holding means is provided between the power supply voltage supply line and the resistor so that the voltage between the voltage holding means and the resistor is maintained unless the value of the power supply voltage exceeds a first predetermined voltage value. Does not exceed the third predetermined value, it is possible to reliably hold the reset signal at a value lower than the third predetermined value even when the value of the power supply voltage is lower than the first predetermined voltage value. it can.

[0010]

Next, a reset circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings, the components denoted by the same reference numerals all indicate the same components.

(First Embodiment) First, a reset circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is an equivalent circuit diagram showing a configuration of the reset circuit of the present embodiment. In the reset circuit of the present embodiment, a resistor 6 and a diode 7 are inserted in parallel between the supply line of the power supply voltage Vcc and the pull-up resistor 2. The diode 7 is connected such that the pull-up resistor 2 side becomes an anode. The resistor 6 and the pull-up resistor 2
The capacitor 5 is inserted between the ground and the ground. The reset signal / RES output from the reset IC 1 is output to a CPU (not shown) or the like provided in the digital circuit, and is enabled to enable writing to a RAM (not shown) storing backup data. Used to deactivate signals. If the reset signal / RES is held at a value lower than the third predetermined value, writing to the RAM becomes impossible.

In the reset circuit of this embodiment, unless the value of the power supply voltage Vcc becomes equal to or higher than the operation guarantee voltage of the reset IC 1, the value of the voltage at the point B is determined by the CR filter including the resistor 6 and the capacitor 5. , The rise of the voltage value at the point B is delayed. Then, in the period A of FIG. 4, the value of the reset signal / RES becomes lower than the third predetermined value, and the above-mentioned RAM remains unwritable.

If the capacitor 5 remains charged when the power is turned on again, the reset circuit of this embodiment does not operate normally. Therefore, the power is turned off and the value of the power supply voltage Vcc is changed from 5 V to 0 V. This is for discharging the voltage held in the capacitor 5 when the voltage drops to

As described above, in the reset circuit of this embodiment, the supply line of the power supply voltage Vcc and the pull-up resistor 2
By providing a CR filter between these points, the rise in the voltage value at point B can be delayed. for that reason,
Even when the value of the power supply voltage Vcc is lower than the operation guarantee voltage value of the reset IC 1, the value of the reset signal / RES is changed to the third value.
Can be reliably held at a value that is lower than the predetermined value of the above-mentioned and is not writable by the RAM.

(Second Embodiment) Next, a reset circuit according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of the reset circuit of the present embodiment.

In the reset circuit of the present embodiment, a PNP transistor 8 which is a semiconductor switching element is provided between the supply line of the power supply voltage Vcc and the pull-up resistor 2, and the emitter is on the supply line side of the power supply voltage Vcc. Has been inserted. Further, a resistor 10 is inserted between the collector of the transistor 8 and the ground, and the base of the transistor 8 is grounded via the resistor 9. Also, the reset signal / RES output from the reset IC 1
Is a RAM in which backup data is stored in addition to a CPU (not shown) provided in a digital circuit.
It is also used to deactivate an enable signal (not shown) that enables writing. If the value of the reset signal / RES is held at a value lower than the third predetermined value, writing to the RAM becomes impossible.

In the reset circuit of this embodiment, the voltage value at point B is 0 V unless the transistor 8 is turned on. The transistor 8 is set so as not to turn on unless the value of the power supply voltage Vcc becomes equal to or higher than the operation guarantee voltage value of the reset IC 1. Therefore, the rise of the reset signal / RES as shown in the period A in FIG. 4 does not occur in the reset circuit of the present embodiment.

When the power supply is turned off and the value of the power supply voltage Vcc decreases, the resistor 10 outputs a reset signal / RE.
This is for setting the value of S to L. Further, in order to increase the value of the voltage Vcc at which the transistor 8 is turned on, a diode can be inserted at a point D between the resistor 9 and the ground as shown in the figure.

As described above, in the reset circuit of this embodiment, the supply line of the power supply voltage Vcc and the pull-up resistor 2
If the value of the power supply voltage Vcc does not become equal to or higher than the operation assurance voltage value of the reset IC 1, the value of the reset signal / RES remains at 0 V. Therefore, in the reset circuit of the present embodiment, even when the value of the power supply voltage is lower than the operation guarantee voltage value of the reset IC 1, the value of the reset signal / RES is stored in the RAM.
Can be reliably held at a value at which writing becomes impossible.

[0020]

As described above, in the reset circuit of the present invention, the power supply voltage is equal to or higher than the first predetermined voltage value by the voltage holding means provided between the power supply voltage supply line and the pull-up resistor. Otherwise, the voltage value at the point of pull-up does not exceed the writable voltage value of the RAM.
Therefore, in the reset circuit of the present invention, even when the value of the power supply voltage is lower than the operation guarantee voltage value of the reset IC, the value of the reset signal is reliably set to a value at which the RAM storing the backed-up data is not writable. Can be held.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a reset circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a reset circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional reset circuit.

FIG. 4 is a graph showing how a reset signal changes when a power supply voltage Vcc rises.

[Explanation of symbols]

 1 Reset IC (TL7705) 2 Pull-up resistor 3, 4 Capacitor 5 Capacitor 6, 9, 10 Resistor 7 Diode 8 Transistor

Claims (3)

[Claims] The power supply voltage is pulled up by a resistor, and is held at a low level when the value of the power supply voltage is equal to or more than the first predetermined value and less than the second predetermined value. A reset circuit for outputting a reset signal which is kept at a low level for a predetermined time from a time when the value of the power supply voltage becomes equal to or more than a second predetermined value and then becomes a high level after the supply of the power supply voltage; Voltage holding means, provided between a line and the resistor, for holding the value of the reset signal at a value lower than a third predetermined value when the value of the power supply voltage is lower than a first predetermined value A reset circuit comprising: 2. The method according to claim 1, wherein the voltage holding unit is configured to control a voltage between the voltage holding unit and the resistor during a period from when the power supply voltage rises to when the value of the power supply voltage reaches the first predetermined value. 2. The reset circuit according to claim 1, wherein the reset circuit is a CR filter that delays a rise in voltage between the voltage holding unit and the resistor so that the value does not exceed the third predetermined value. 3. The reset circuit according to claim 1, wherein said voltage holding means is a semiconductor switching element that is turned on when a value of said power supply voltage becomes equal to or more than said first predetermined value.