JPS6327800B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, particularly for testing programmable read-only memories and their write circuits.
Concerning integrated circuits including PNPN circuits.

With the recent development of information processing, programmable read-only memories (hereinafter referred to as P-ROMs) have come into widespread use. P-ROMs are particularly widely used because they can be programmed by electrical writing.

FIG. 1 is a block diagram of an example of a conventional P-ROM.

As shown in the figure, P-ROM is an address circuit
ADD, selection circuit DD, fixed memory element MC, chip enable circuit CE, output circuit OC, write circuit PB
These are manufactured by the manufacturer, shipped, delivered to the user, and then written by the user. Therefore, the manufacturer cannot actually write, and testing to see whether the desired writing can be performed correctly, which is very important for P-ROMs, becomes insufficient. Conventionally, the test of whether or not the desired write can be performed correctly, that is, the test of whether the selection circuit has the ability to absorb the write current, has been carried out in the past.
In P-ROM, the configuration is as shown in Figure 2. In other words, a dummy cell DC and a PNPN circuit 10 are connected to the selection circuit, and a current equivalent to the write current is applied from the test terminal T. Current flows into the selection circuit through the PNPN circuit 10 and the dummy cell DC. By testing the potential of the test terminal T at that time, it is possible to test whether the selection circuit has the ability to absorb the write current. Normally, in a P-ROM, the test terminal T is shared with the input terminal in order to save on the number of terminals. (For example, with a chip enable terminal) As for the PNPN circuit 10, a simple circuit as shown in FIG. 3 is used so as not to increase the chip area. That is, it is composed of PNP transistor Q ₁ and NPN transistor Q ₂ .
A PNPN element, an NPN Darlington transistor Q ₃ with the above NPN transistor Q ₂ as the first stage, and a PNP transistor Q ₁ inserted between the base and collector to automatically turn on the PNPN circuit when the input potential exceeds a certain potential. zener diode
Composed by D ₁ . In this PNPN circuit 10, when the input potential (potential on the emitter side of the PNP transistor _Q1 ) rises, the base potential of the PNP transistor _Q1 also rises, and when the potential exceeds the Zener potential of the Zener diode _D1 , the Zener diode _D1 Breakdown NPN transistor _Q2
A current can flow to the base of the transistor Q2, and the NPN transistor _Q2 is turned on, and the PPNN circuit 10 is turned on.
However, since the Zener voltage is normally 7V or more, even if a potential of 7V or less is applied to the input T _IN , the PNPN circuit 10
should not be turned on. However, if noise with a steep rise (several ns) is applied to the test terminal T,
The base of the PNP transistor Q ₁ rises to approximately the same level as the input potential, and a transient current i _t at this time flows from the emitter to the base of the PNP transistor Q ₁ . i _t flows to R ₁ through the junction capacitance of the Zener diode and the BC capacitance of the NPN transistor, and can turn on the NPN transistor Q ₂ . Also, the transient current i _t
is also the base current of PNP transistor _Q1 .
A current h _fe times that of the PNP transistor Q ₁ flows as a collector current, turning on the NPN transistor Q ₂ . Due to these two effects, in the PNPN circuit 10 installed for the purpose of testing the characteristics of the write circuit PB, when a steep noise is applied to the test terminal T, the PPNN circuit 10 turns on, and the current flows to the dummy cell.
The drawback was that it could flow into the driver through DC and cause malfunction.

The present invention eliminates the above drawbacks and provides an integrated circuit including a PNPN circuit for testing read-only write circuits with improved noise immunity.

An integrated circuit of the present invention includes a fixed memory element that can be written semi-permanently by flowing a write current, a write circuit for selectively flowing a write current into the fixed memory element, and a plurality of address input terminals. an address circuit and a selection circuit for selecting the fixed storage element, an output circuit for outputting information of the storage element, and a chip enable terminal for selecting or non-selecting the output circuit using a plurality of chip enable terminals. Circuit, PNP transistor and corresponding
a PNPN circuit configured to include an NPN transistor whose collector is connected to the base of the PNP transistor and whose base is connected to the collector of the PNP transistor, and for testing the characteristics of the selection circuit;
and a control circuit connected to the base of the NPN transistor of the PNPN circuit.

The control circuit is controlled by a plurality of address terminals or a plurality of chip enable terminals.

Next, embodiments of the present invention will be described using the drawings.

FIG. 4 is a block diagram of one embodiment of the present invention.

This embodiment consists of a fixed memory element MC that can be written semi-permanently by flowing a write current, a write circuit PB for selectively flowing a write current into this fixed memory terminal MC, and a plurality of address inputs. Address circuit ADD and selection circuit DD for selecting fixed memory element MC with a terminal, and fixed memory element
An output circuit OC for outputting MC information, a chip enable circuit CE for selecting or deselecting the output circuit OC using multiple chip enable terminals, a PNP transistor Q ₁ and a base of this PNP transistor Q ₁ . The collector is connected and the base is connected to the collector of PNP transistor _Q1 .
a PNPN circuit 10 configured to include an NPN transistor _Q2 and for testing the characteristics of the selection circuit DD;
The control circuit 11 is connected to the base of the NPN transistor _Q2 of the PNPN circuit 10.

Next, the operation of this embodiment will be explained.

When testing the properties of the selection circuit DD, the control circuit 11
When PNPN circuit 1 is inactivated and a current similar to the write current is applied to test terminal T as described above,
Current flows into the selection circuit DD through 0 and the dummy cell DC. By testing the potential of the test terminal T at that time, the characteristics of the selection circuit DD can be tested. and,
At times other than testing, the control circuit 11 sets the collector of the PNP transistor Q ₁ to approximately the ground level, so that even if steep noise is applied to the test terminal T, the transient current i _t is transferred from the emitter of the PNP transistor Q ₁ to the base of the Zener diode. It flows into the control circuit 11 through D ₁ and does not flow into the resistor R ₁ , so that the NPN transistor Q ₂ is not turned on. In other words, the PNPN circuit 10 cannot be turned on.

When testing the characteristics of the selection circuit DD, the control circuit 11
By applying a potential higher than the breakdown of Zener diode _D2 (e.g. 10V) to the input terminal T _{IN of} , NPN transistor _Q6 turns on,
NPN transistors Q ₄ and Q ₅ are turned off. This means that the control circuit 11 is irrelevant to the PNPN circuit 10, and when a current approximately equivalent to the write current is applied to the test terminal T connected to the PPNN circuit 10,
The signal flows into the selection circuit through the PNPN circuit 10 and the dummy cell DC, and the desired characteristics of the selection circuit DD can be tested. The full voltage of logic "1" and "0" is applied to the input terminal T _IN of the control circuit 11 when testing the characteristics of the selection circuit DD, that is, when testing other alternating current, direct current, etc. manufactured by the manufacturer, and when using it on the user's side. Even if a range (typically -0.5V to +5.5V) is applied
NPN transistor Q ₆ remains off, and NPN transistors Q ₄ and Q ₅ remain on. At that time, even if a sharp rising noise is applied to the test terminal T connected to the PNPN circuit 10, the transient current flows from the emitter to the base of the PNP transistor _Q1 , and then flows into the NPN transistor _Q4 through the Zener diode _D1 . The PNPN circuit 10 installed for the purpose of testing the characteristics of the selection circuit DD is never turned on.

As explained in detail above, according to the present invention,
The PNPN circuit, which was set up to test the characteristics of the selection circuit that writes to the fixed memory element, will not turn on even if a sharp rise noise enters the circuit.
The effect is significant because an integrated circuit including a PNPN circuit and a programmable read-only memory is obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an example of a conventional P-ROM, and Figure 2 is a P-ROM with a selection circuit test circuit added.
A block diagram of the ROM, a circuit diagram of an example of a detailed circuit of the PNPN circuit shown in FIG. 3, and FIG. 4 a block diagram of an embodiment of the present invention. 10...PNPN circuit, 11...control circuit, A ₁
~A _o ...Address terminal, _D1 , _D2 ...Zener diode, _O1 ~ _On ...Output terminal, _Q1 ...PNP transistor, _Q2 ~ _Q6 ...NPN transistor,
R ₁ , R ₂ ... Resistance, T ... Test terminal, T _IN ... Input terminal, ADD ... Address circuit, CE ... Chip enable circuit, CE ₁ to CE _j ... Chip enable terminal, DC ... Dummy cell , DD... selection circuit,
MC...Fixed memory element, OC...Output circuit, PB...
...Writing circuit.

Claims (1)

[Claims] 1. A fixed memory element that can be written semi-permanently by flowing a write current; a write circuit for selectively flowing a write current into the fixed memory element;
an address circuit and a selection circuit for selecting the fixed storage element using a plurality of address input terminals, an output circuit for outputting information of the storage element, and selecting or non-selection of the output circuit using a plurality of chip enable terminals. The chip enable circuit that normalizes the chip and the emitter connected to the test signal input terminal
Testing the characteristics of the selection circuit configured to include a PNP transistor and an NPN transistor whose collector is connected to the base of the PNP transistor and whose base is connected to the collector of the PNP transistor.
An integrated circuit comprising: a PNPN circuit; and a control circuit that sets the base of the NPN transistor of the PNPN circuit to a low voltage.