JPS6181667A - Transistor device and making thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to semiconductor devices, more specifically, MOS
Concerning the manufacture of VLSIt-transistors.

Prior Art and Problems In high-density DRAM arrays such as 1 megabit devices,
MOS access transistors with molybdenum gates and molybdenum word lines are used because molybdenum has a much smaller resistance value than polysilicon. It is also advantageous to silicide the surfaces of the source/drain (moat) regions for these access transistors or coat them with a crat layer to reduce the series resistance of these regions. However, when attempting to perform both a metal gate process and a direct reaction coated moat process on the same device, the chemicals used to strip unreacted metal in the coated moat process may be used to remove the metal gate encapsulation layer. The problem arose because metal gate materials tend to erode through defects. Theoretically, this problem could be solved by using an acid that would strip the unreacted titanium metal and would not attack the molybdenum metal.

Examples include dilute hydrochloric acid or dilute sulfuric acid. In practice, it has been found that methods using selective acids that take into account the gate and coating materials do not work for the following reasons. The metal deposited for the moat coating reacts to form a silicide over the exposed silicon areas, but the titanium reacts with the furnace gases used in the silicification operation as well as with the plasma oxide encapsulant. (no pure metal on top of the oxide region).

Dilute hydrochloric acid does not effectively remove furnace-treated titanium. The dilute sulfuric acid removes the furnace-treated titanium metal, but stops at the conductive interfacial layer formed at the interface of the plasma oxide encapsulation.

The main purpose of Nobino's invention is to solve the problem of VLSI MO8 devices, especially metal gate coated mote devices! It is an object of the present invention to provide an improved method of manufacturing. Another object is to provide a method for etching unreacted refractory metal from the surface of a silicon slice without undesirably etching the encapsulated refractory metal gate.

In one embodiment of the invention, the key is a two-layer glass encapsulation (or equivalently, a doping concentration By using a doped glass (continuously changed doped glass), it becomes possible to remove the furnace-treated titanium using only dilute sulfuric acid. When depositing and densifying an additional layer of phosphorus-doped glass (phosphosilicate glass), no formation of a conductive interfacial layer (which is not removed by the sulfuric acid, as previously mentioned) occurs. This 2
The overlayer feature is in contrast to previously used process flows that use only undoped plasma oxide layers for both the cap oxide and sidewall oxide layers. In processes that do not use a cap oxide, such as the Selfaline silicide process, the method of the present invention helps eliminate commonly occurring gate-to-drain shorts (due to conductive interface layers).

Although the novel features and disadvantages considered to be unique to this invention are set forth in the claims, the invention itself, as well as other features and advantages, are best understood from the following detailed description of the drawings. Good morning.

EXAMPLE 1 With reference to FIGS. 1-5, a method of fabricating a molybdenum gate transistor with silicided source/drain regions will be described. As shown in FIG. 1, a silicon substrate 10 is coated with a thin thermal oxide 11 that acts as a gate oxide.

The oxide 11 may have a thickness of 200 to 300 mm, for example. A molybdenum layer 12 is deposited on top of the gate oxide 11 to a thickness of approximately 2.500 nm. The molybdenum is capped with an oxide layer 13 by deposition of silicon oxide.
cover with The gate is then defined by conventional photolithographic patterning, leaving a transistor gate 14 having dimensions of approximately 1.5 or 2 microns, as shown in FIG. The surface is coated with another silicon oxide coating 16 and this coating is subjected to an anisotropic etch such as an RIE etch (reactive ion etch) to form a sidewall oxide 17 as shown in FIG.
leave only

An n+ implant is now performed using arsenic as a dopant to form the source/drain region 18, as seen in FIG.
make. The region 141B is also called a moat region, and is then silicided or covered with a cladding, as will be explained later. First, some measure must be taken to protect the molybdenum 12 from reacting with the etchant that will be used later.

In this invention, one method of protecting the molybdenum is to use vapor densification (5teal densification) at this point in the process to more fully bond the separately deposited cap oxide 13 and sidewall plasma oxide 17.
Catton) process is added. This seals the joint 19. Steam densification is, for example, 90
It can be carried out in steam for 9 minutes at 0°C.

As another example, one or both of the plasma-deposited cap oxide 13 or the sidewall oxide 17 may be replaced with a very thin but continuous plasma oxide (m), which replaces the previously bare molybdenum in a furnace. by replacing the layered structure with a thicker layer of oxide by high temperature and low pressure chemical vapor deposition.
Further, higher quality oxides can be obtained. The structure in that case is as shown in FIG. Figure 4 is similar to Figure 3, but
It is expanded. In this figure, layers 13 and 17 are
113a, 13b and 17a.

It appears as 17b.

The double layer configuration just described can also be achieved with phosphorous-doped atmospheric CvD oxides 13 and 17 (instead of plasma deposited oxides). This CVD
The oxide, also known as phosphosilicate glass or PSG, can be deposited using multiple bath deposition equipment;
Thick MLO.

That is, one pass is used instead of the usual multiple passes used with multilevel oxides. This device has the advantage of providing better control than that provided by single layer thick MLO devices used for such single layers. The target is plasma deposited with a thickness of 2.000 or 1.500 P over 1.13a or 17a respectively.
This is the SG layer 13b or 17b. This gives a total thickness of sidewall oxide 17 of 3.000 mm. The cap oxide 13 is about 2,000 in two layers.

Using PSG glass as the second layer (1) results in less stress and less tendency to strain cracking;
(This has the advantage of assisting in gettering of sodium or other mobile ions that may be involved in processing metal gates.)

Continuing the process, a thin coating 20 of titanium is deposited and heat is applied to the slice in a furnace to cause the titanium to react with the silicon and cause silicification on the surface of the moat area, as seen in FIG. Make Titanium 21. Remove the remaining titanium 20 on top of gate 15 using only dilute sulfuric acid.

Although the invention has been described in terms of embodiments, this description should not be construed as limiting the invention.

From the above description, various modifications of this embodiment, as well as other embodiments of the invention, will be readily apparent to those skilled in the art.

It is therefore intended that the appended claims cover all such modifications and embodiments as fall within the scope of this invention.

[Brief explanation of drawings]

1-5 are greatly enlarged side cross-sectional views of very small portions of semiconductor slices at various stages of the manufacturing process of the present invention. Explanation of symbols 10: Silicon substrate 12: Molybdenum layer 13: Cap oxide layer 14: Gate 17: Sidewall oxide 20: Titanium coating 21: Titanium silicide

Claims (20)

[Claims] (1) Forming a gate electrode on the surface of the silicon body and providing an oxide coating on the gate electrode, depositing the oxide and anisotropically etching the sidewalls of the gate electrode. forming an oxide coating on the top and sidewalls of the gate electrode, wherein the oxide coatings on the top and sidewalls of the gate electrode are made by separate depositions, such that the interface between the oxide coatings is non-permeable; depositing a metal layer on the surface of the body and reacting the metal with the silicon on the surface of the body in areas not covered by the gate electrode and sidewall oxide; and then removing unreacted metal from the surface of the body without disturbing the gate electrode by etching. (2) In the method for manufacturing a transistor device according to claim 1, the gate electrode is made of a high melting point metal,
A method for manufacturing a transistor device, wherein the metal layers are made of different high melting point metals. (3) In the method for manufacturing a transistor device according to claim 1, each oxide coating is coated with the first plasma.
A method of making a transistor device including a deposit coating and a second phosphorous-doped CVD oxide coating. (4) A method for manufacturing a transistor device according to claim 1, wherein the metal layer is titanium. (5) In the method for manufacturing a transistor device according to claim 4, the etching step uses diluted sulfuric acid. (6) In the method for manufacturing a transistor device according to claim 1, the gate electrode is made of molybdenum,
A method for manufacturing a transistor device, wherein the metal layer is titanium, and the etching step uses sulfuric acid. (7) A method for manufacturing a transistor device according to claim 6, wherein the oxide coating is a two-layered plasma deposit layer and a phosphosilicate glass layer. (8) forming an electrode on the surface of the silicon body and providing an oxide coating on the top of the electrode, depositing the oxide and anisotropically etching the oxide coating on the sidewalls of the electrode; forming an oxide coating on the top and sidewalls of the electrode, made by separate depositions, but sealed in a non-permeable manner at the interface between the oxide coatings; depositing a layer of conductive material on the surface of the body and reacting the material with the silicon on the surface of the body in areas not covered by the electrode and sidewall oxide; A method for manufacturing a semiconductor device, including the step of thereafter selectively etching the conductive material to remove unreacted conductive material from the surface without etching the electrode. (9) The method for manufacturing a semiconductor device according to claim 8, wherein the electrode is a high melting point metal, and the conductive material layers are different high melting point metals. (10) In the method of manufacturing a semiconductor device according to claim 8, each oxide coating includes a first plasma deposited coating and a second phosphorous-doped CVD oxide coating. Manufacturing method for semiconductor devices. (11) The method for manufacturing a semiconductor device according to claim 8, wherein the conductive material layer is titanium. (12) The method for manufacturing a semiconductor device according to claim 11, in which the etching step uses diluted sulfuric acid. (13) The method for manufacturing a semiconductor device according to claim 8, wherein the electrode is made of molybdenum, the layer of conductive material is titanium, and the etching step uses sulfuric acid. (14) The method for manufacturing a semiconductor device according to claim 13, wherein the oxide coating is two layers: a plasma deposit layer and a phosphosilicate glass layer. (15) a gate electrode on the surface of a silicon body with an oxide coating on its top; a sidewall oxide coating only on the sidewalls of the gate electrode; and on the surface of the body. an oxide coating on the top and sidewalls of the gate electrode sealing the separate coatings such that the interface between the oxide coatings is non-permeable; , reacting with the gate electrode and the silicon of the surface in areas not covered by the sidewall oxide. (16) In the transistor device according to claim 15, the gate electrode is made of a high melting point metal,
A transistor device in which the metal layers are different high melting point metals. (17) A transistor device according to claim 15, wherein each oxide coating includes a first plasma deposited coating and a second phosphorous-doped CVD oxide coating. . (18) The transistor device according to claim 15, wherein the metal layer is titanium. (19) The transistor device according to claim 15, wherein the gate electrode is made of molybdenum and the metal layer is made of titanium. (20) The transistor device according to claim 19, wherein the oxide coating includes two layers: a plasma deposit layer and a phosphosilicate glass layer.