JPH0620078B2 - Transistor device manufacturing method and semiconductor device manufacturing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, more specifically, a MOS.
Related to the manufacture of VLSI transistors.

Conventional Technology and Problems In a high-density DRAM array such as a 1-megabit device,
Since the resistance value of molybdenum is smaller than that of polysilicon, a MOS access transistor having a molybdenum gate and a molybdenum word line are used.
Similarly, it is advantageous to silicide or coat the surface of the source / drain (moat) regions for these access transistors to reduce the series resistance of these regions. However, when attempting to perform both a metal gate process and a direct reactive coating moat process on the same device, the chemical used to strip unreacted metal in the coated moat process is The problem arises because there is a risk of eroding the metal gate material through the defects of. Theoretically, this problem can be solved by using an acid that strips unreacted metallic titanium such that it does not attack metallic molybdenum.
As an example, dilute hydrochloric acid or dilute sulfuric acid is considered. In practice, it has been found that the selective acid method taking into account the gate material and the coating material is not successful for the following reasons. The metal deposited for the moat coating reacts to form a silicide on the exposed silicon areas, but titanium is desired to react with the furnace gases used in the silicidation operation as well as the plasma oxide encapsulant. As is the case with pure metal on the oxide region. Diluted hydrochloric acid does not effectively remove furnace treated titanium.
Dilute sulfuric acid removes the titanium metal treated in the furnace, but stays at the conductive interface layer formed at the interface of the plasma oxide encapsulation.

Means and Actions for Solving the Problems A main object of the present invention is to provide an improved method of manufacturing VLSI MOS devices, especially metal gate coated moat devices. Another object is to provide a method of etching unreacted refractory metal from the surface of a silicon slice without undesired etching of the encapsulated refractory metal gate.

In one embodiment of the present invention, the essence is that two layers of glass encapsulation (or equivalent, but with a doping concentration of lower layer undoped glass and upper layer phosphorus-doped glass) are used. It is possible to remove the titanium treated in the furnace using only dilute sulfuric acid, by using a doped glass with a continuous change of. When depositing and densifying an additional layer of phosphorus-doped glass (phosphosilicate glass), the formation of a conductive interface layer (which is not removed by sulfuric acid as previously mentioned) does not occur . This dual layer feature contrasts with previously used process flows that use only undoped plasma oxide layers for both the cap oxide and sidewall oxide layers. In processes that do not use cap oxides, such as the self-aligned silicide process, the method of the present invention helps eliminate gate-drain shorts (due to the conductive interface layer) that normally occur.

While the novel features believed characteristic of the invention are set forth in the appended claims, the invention itself, as well as other features and advantages, will be best understood from the following detailed description of the drawings.

EXAMPLE A method of manufacturing a molybdenum gate transistor having silicided source / drain regions will be described with reference to FIGS. As shown in FIG. 1, a silicon substrate 10 is coated with a thin thermal oxide 11 which acts as a gate oxide. The oxide 11 may have a thickness of 200 to 300Å, for example. A molybdenum layer 12 is deposited over the gate oxide 11 to a thickness of approximately 2,500 Å.
A cap oxide layer 13 covers the molybdenum by a silicon oxide deposition. Next, as shown in FIG.
Conventional photolithographic patterning defines the gate, leaving a transistor gate 14 with dimensions of approximately 1.5 or 2 microns. The surface is coated with another silicon oxide coating 16 and this coating is subjected to an anisotropic etch such as a RIE etch (reactive ion etch), leaving only sidewall oxide 17, as shown in FIG.

Using arsenic as a dopant, an n ⁺ implant is performed here, as shown in FIG.
make. Region 18, also referred to as the moat region, is then silicidated or cladding coated, as described below.
First, some measures must be taken to protect molybdenum 12 from reacting with the etchant used thereafter.

In the present invention, one method of protecting molybdenum is to more fully combine the separately deposited cap oxide 13 and sidewall plasma oxide 17 so that steam densification at this point in the process occurs. It is to add a process. The joint 19 is thereby sealed. The steam densification can be carried out in steam at 900 ° C. for 9 minutes, for example.

As another example, one or both of the plasma deposited cap oxide 13 and / or the sidewall oxide 17 may be provided with a very thin but continuous plasma oxide layer (which may be molybdenum which was previously bare). , And a thicker layer of oxide by high temperature low pressure chemical vapor deposition.
A higher quality oxide is obtained. The structure in that case is as shown in FIG. 4 is similar to FIG. 3, but
It has been expanded. In this figure, layers 13 and 17 appear as double layers 13a, 13b and 17a, 17b.

The bilayer formation just described can also be achieved with phosphorus doped atmospheric pressure CVD oxides 13 and 17 (instead of plasma deposited oxides). This CVD
Oxide, also called phosphosilicate glass or PSG, can be deposited using a multi-pass deposition system,
Use one pass instead of the normal multi-pass used for thick MLO, or multi-level oxide. This device
There is the advantage that better control can be obtained compared to the control obtained with a single layer thick MLO device used for such a single layer. Targets are 1,000 Å each
Or a thickness of 2,000Å or 1, on the plasma deposited deposit oxide layer 13a or 17a of 500Å
It is the PSG layer 13b or 17b of 500Å. This results in a total thickness of sidewall oxide 17 of 3,000 Å. The cap oxide 13 is two layers and has a thickness of about 2,000Å.

If PSG glass is used as the second layer, (1) there will be less stress and less tendency to crack, (2)
It has the advantage of being able to assist the gettering action of sodium or other mobile ions that may be involved in the processing of metal gates.

Continuing the process, as seen in FIG. 5, a thin coating 20 of titanium is deposited and heat is applied to the slices in a furnace to react the titanium with silicon and silicify the surface of the moat area. Make Titanium 21. Only dilute sulfuric acid is used to remove the titanium 20 remaining on top of the gate 15.

Although the invention has been described with reference to embodiments, this description should not be construed as limiting the invention. From the above description, various modifications of this embodiment as well as other embodiments of the present invention will be readily apparent to those skilled in the art. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and embodiments that fall within the scope of this invention.

[Brief description of drawings]

1 through 5 are greatly enlarged side cross-sectional views of a tiny portion of a semiconductor slice at various stages of the manufacturing process of the present invention. DESCRIPTION OF SYMBOLS 10: Silicon substrate 12: Molybdenum layer 13: Cap oxide layer 14: Gate 17: Side wall oxide 20: Titanium coating 21: Titanium silicide

Claims (14)

[Claims] 1. A step of forming a gate electrode on a surface of a silicon body and providing an oxide coating on the gate electrode; depositing an oxide and performing anisotropic etching to form a sidewall of the gate electrode. Forming an oxide coating on the top surface of the gate electrode formed by separate deposition, and sealing the oxide coating on the sidewalls so that it is impermeable at the interface between the oxide coatings. Depositing a metal layer on the surface of the body and reacting the metal with silicon on the surface of the body in areas not covered by the gate electrode as well as sidewall oxides, then etching Thus, a method for manufacturing a transistor device, including the step of removing unreacted metal from the surface of the body without disturbing the gate electrode. 2. The method for manufacturing a transistor device according to claim 1, wherein the gate electrode is a refractory metal and the metal layer is a different refractory metal. 3. A method of manufacturing a transistor device according to claim 1, wherein each oxide coating is a plasma
A method of making a transistor device including a deposit coating and a phosphorus-doped CVD oxide coating. 4. A method for manufacturing a transistor device according to claim 1, wherein the metal layer is titanium. 5. The method for manufacturing a transistor device according to claim 4, wherein the etching step uses diluted sulfuric acid. 6. The method of manufacturing a transistor device according to claim 1, wherein the gate electrode is molybdenum, the metal layer is titanium, and the etching step uses sulfuric acid. . 7. A method of making a device as claimed in claim 6 wherein the oxide coating is a two layer plasma deposit layer and a phosphorus doped CVD oxide coating. 8. Forming an electrode on the surface of a silicon body and providing an oxide coating on the top of the electrode, oxidizing the oxide on the sidewalls of the electrode by depositing and anisotropic etching. Forming an oxide coating, sealing oxide coatings on top and sidewalls of the electrodes made by separate depositions such that they are impermeable at the interface between the oxide coatings, Depositing a layer of conductive material on the surface of the body and reacting the material with silicon on the surface of the body in areas not covered by the electrodes as well as sidewall oxides; A method of manufacturing a semiconductor device, comprising a step of removing unreacted conductive material from the surface by selective etching without etching the electrode. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the electrodes are refractory metals and the layers of the conductive material are refractory metals different from each other. 10. A method of making a semiconductor device according to claim 8 wherein each oxide coating comprises a plasma deposit coating and a phosphorus doped CVD oxide coating. . 11. The method for manufacturing a semiconductor device according to claim 8, wherein the conductive material layer is titanium. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the etching step uses diluted sulfuric acid. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the electrode is molybdenum, the conductive material layer is titanium, and the etching step uses sulfuric acid. Manufacturing method. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the oxide coating is two layers of a plasma deposit layer and a phosphorus-doped CVD oxide coating. .