JPS63299273A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63299273A JPS63299273A JP13146087A JP13146087A JPS63299273A JP S63299273 A JPS63299273 A JP S63299273A JP 13146087 A JP13146087 A JP 13146087A JP 13146087 A JP13146087 A JP 13146087A JP S63299273 A JPS63299273 A JP S63299273A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- atmosphere
- mask
- treated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000001257 hydrogen Substances 0.000 claims abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 239000007789 gas Substances 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- 229910052721 tungsten Inorganic materials 0.000 description 16
- 229910052750 molybdenum Inorganic materials 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052783 alkali metal Inorganic materials 0.000 description 2
- 150000001340 alkali metals Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
アンモニア（ＮＨ３）雰囲気中でタングステン（Ｗ）、
モリブデン（Ｍｏ）の如き純粋高融点金属の側面を含む
全表面を窒化し、Ｗ＋ Ｍｏの窒化物を残し、水素雰囲
気中で熱処理を行い、後の熱酸化工程などにおけるＷ＋
Ｍｏの耐酸化性を向上させ、かつ、剥離を防止する。[Detailed description of the invention] [Summary] Tungsten (W) in an ammonia (NH3) atmosphere,
The entire surface of a pure high-melting point metal such as molybdenum (Mo), including the side surfaces, is nitrided, leaving a W+ Mo nitride, and heat-treated in a hydrogen atmosphere to remove W+ during the subsequent thermal oxidation process.
Improves the oxidation resistance of Mo and prevents peeling.
本発明は半導体装置の製造方法、特にゲート電極や配線
をＷなどの高融点金属を用いて作るにおいて、後工程で
の熱酸化においてＷなどの剥離を防止するために、ゲー
ト電極の側面を含む全表面に窒化膜を形成し、それを残
し、しかる後に水素雰囲気中で熱処理をなす方法に関す
る。The present invention relates to a method for manufacturing a semiconductor device, particularly in manufacturing gate electrodes and wiring using a high melting point metal such as W, in which side surfaces of the gate electrode are included in order to prevent peeling of W etc. during thermal oxidation in a later process. The present invention relates to a method of forming a nitride film on the entire surface, leaving it as it is, and then subjecting it to heat treatment in a hydrogen atmosphere.
ＭＯ５型半導体装置では、従来ゲート電極に多結晶シリ
コンや各種の金属珪化物が使われていたがこれらの多結
晶シリコンや金属珪化物は配線にも使われるようになっ
た。半導体装置の高集積化に伴い、電極や配線が微細化
すると、抵抗が増大し動作速度が遅くなる。In MO5 type semiconductor devices, polycrystalline silicon and various metal silicides have conventionally been used for gate electrodes, but these polycrystalline silicon and metal silicides have also come to be used for wiring. As semiconductor devices become more highly integrated, electrodes and wiring become finer, resulting in increased resistance and slower operation speed.
ＷやＭｏなどの純粋高融点金属は、多結晶シリコンや金
属珪化物に比べ電気抵抗率が小であるのでゲート電極、
配線などにＷやＭＯを使用する利点は大であり、例えば
ＭＯ３型半導体装置のゲート電極にＷを使用する技術が
研究されている。Pure high-melting point metals such as W and Mo have lower electrical resistivity than polycrystalline silicon and metal silicides, so they can be used for gate electrodes,
There are great advantages to using W or MO for wiring, etc., and for example, techniques for using W for gate electrodes of MO3 type semiconductor devices are being researched.
しかし、ＷやＭｏは酸化されやすいために、それを用い
る半導体素子の製造においては、その酸化を防止するこ
とが正要な課題である。例えばＷでゲート電極を形成し
たものに酸素雰囲気中で熱処理（９００℃＋ ０２
＋ ３０分）をした場合、熱処理によって匈０３となっ
た膜は剥離してその後のプロセスで使えなくなる。However, since W and Mo are easily oxidized, it is important to prevent oxidation in manufacturing semiconductor devices using them. For example, a gate electrode formed of W is heat-treated in an oxygen atmosphere (900°C + 02°C).
+ 30 minutes), the film that has become a layer 03 due to the heat treatment will peel off and become unusable in subsequent processes.
ＷやＭｏの酸化を防止するための従来例を第３図の断面
図を参照して説明すると、Ｗで作ったゲート電極の上面
および側面を高融点金属の珪化物で覆う方法が公にされ
（特開昭５６−１５０７０号公報）、この方法において
は、シリコン（Ｓｔ）基板３１上に絶縁膜（５ｉ０２膜
）３２を介してＷのゲート電極３３が形成され、ゲート
電極３３の上面と側面はＷＳｉ２膜３４と３５で覆われ
てなるゲート電極が提供される。A conventional method for preventing the oxidation of W and Mo will be explained with reference to the cross-sectional view in Fig. 3. A method has been publicly disclosed in which the top and side surfaces of a gate electrode made of W are covered with a silicide of a high-melting point metal. (Japanese Unexamined Patent Publication No. 56-15070), in this method, a W gate electrode 33 is formed on a silicon (St) substrate 31 with an insulating film (5i02 film) 32 interposed therebetween. A gate electrode covered with WSi2 films 34 and 35 is provided.
さらには、Ｗのゲート電極の表面を二酸化シリコン（５
ｉ０２ ）膜、窒化シリコン（Ｓｉ３Ｎｑ膜）などの絶
縁膜で覆うことによりＷやＭＯの酸化を防止する方法も
知られている（特開昭４８−２２２８８号公報）。Furthermore, the surface of the W gate electrode was coated with silicon dioxide (5
A method of preventing oxidation of W or MO by covering it with an insulating film such as i02) film or silicon nitride (Si3Nq film) is also known (Japanese Unexamined Patent Publication No. 48-22288).
しかし、ゲート電極の側壁に上記した珪化物や絶縁物を
残すためには、ゲート電極形成用のエツチングを行った
後に、珪化物や絶縁物の側壁構成用の膜の堆積とりアク
ティブ・イオンエツチング（Ｒ，１，Ｅ、）による異方
性エツチングを行わなければならず、工程が増しコスト
が高くなる問題がある。However, in order to leave the above-mentioned silicide or insulator on the sidewalls of the gate electrode, after performing the etching for forming the gate electrode, active ion etching ( R,1,E,) must be anisotropically etched, which increases the number of steps and increases costs.
他方、酸素分圧を制御することによって、ＷやＭｏを酸
化させることなくＳｔ基板のみを酸化させる方法も公に
されているが（特開昭５９−１３２１３６号公報）、水
素と水蒸気の分圧を選ぶについて難しい問題がある。On the other hand, a method has been published in which only the St substrate is oxidized without oxidizing W or Mo by controlling the oxygen partial pressure (Japanese Unexamined Patent Publication No. 132136/1982), but the partial pressure of hydrogen and water vapor is There is a difficult problem in choosing.
本発明はこのような点に鑑みて創作されたもので、耐酸
化性をもったゲート電極を具備した半導体装置の製造に
おいて、ゲート電極の酸化と剥離を防止する方法を提供
することを目的とする・〔問題点を解決するための手段
〕
第１図は本発明実施例断面図で、図中、１１はシリコン
基板、１２はゲート絶縁膜（ＳｉＯ＋膜）、１３はＷの
ゲート電極、１４はＷの窒化膜（ＷＮ膜）、１５は５ｔ
Ｏ２膜、１６は拡散層、１７は絶縁膜（ＰＳＧ膜）、１
８はシリコン基板とのコンタクト部、１９はゲート電極
とのコンタクト部、２０はアルミニウム（Ａｌ）配線で
ある。The present invention was created in view of the above points, and an object of the present invention is to provide a method for preventing oxidation and peeling of a gate electrode in manufacturing a semiconductor device equipped with a gate electrode having oxidation resistance.・[Means for solving the problem] FIG. 1 is a cross-sectional view of an embodiment of the present invention, in which 11 is a silicon substrate, 12 is a gate insulating film (SiO+ film), 13 is a W gate electrode, and 14 is W nitride film (WN film), 15 is 5t
O2 film, 16 is a diffusion layer, 17 is an insulating film (PSG film), 1
8 is a contact portion with the silicon substrate, 19 is a contact portion with the gate electrode, and 20 is an aluminum (Al) wiring.
本発明の第１実施例では、Ｗを用いたゲート電極１３を
バターニングした後に、ＮＨ３雰囲気中で熱処理を行い
、ゲート電極１３の表面（上面および側面）を窒化する
ことによってＷＮＮ膜種４形成されてなり、このＷＮＮ
膜種４後工程の熱処理において−０３となってもそれの
剥離を防止する。In the first embodiment of the present invention, after patterning the gate electrode 13 using W, heat treatment is performed in an NH3 atmosphere to nitride the surface (upper surface and side surfaces) of the gate electrode 13, thereby forming the WNN film type 4. This WNN
Film Type 4 Prevents peeling even if the temperature reaches -03 in the post-process heat treatment.
ＷはＮ２中では１０００℃でも容易に窒化しないのであ
るが、ＮＨ３中では４００〜８５０℃で窒化する。W does not easily nitride in N2 even at 1000°C, but nitrides in NH3 at 400 to 850°C.
−Ｎは酸化の進行を遅らせるので、Ｓｉ基板１１を熱酸
化して３００人（７＞ ５ｉ０２ ］ＩＷ１５を形成す
る工程においてＷのゲート電極１３には変化が認められ
なかった。Since -N retards the progress of oxidation, no change was observed in the W gate electrode 13 during the process of thermally oxidizing the Si substrate 11 to form 300 (7>5i02) IW15.
以下、図面を参照して本発明実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
再び第１図に戻ると、同図ｆａ）に示されるＭＯＳ型半
導体素子のゲート絶縁膜（ＳｉＯ２膜）１２の成長まで
は通常のＭＯＳ型半導体素子を作成する場合と同様であ
る。次いで、ゲート電極用のＷをスパッタ法によって２
０００人の厚さに堆積する。このＷの上に塗布したレジ
ストをバターニングしてレジストマスク２１を作り、そ
れをマスクにし、エツチングガスにＳＦｓを用いてリア
クティブ・イオン・エツチングを行い、図示したＷのゲ
ート電極１３を形成する。Returning to FIG. 1 again, the process up to the growth of the gate insulating film (SiO2 film) 12 of the MOS type semiconductor element shown in fa) in the figure is the same as in the case of manufacturing a normal MOS type semiconductor element. Next, 2 W for the gate electrode was applied by sputtering.
Deposited to a thickness of 000 people. The resist coated on this W is buttered to form a resist mask 21, and using this as a mask, reactive ion etching is performed using SFs as an etching gas to form the W gate electrode 13 shown in the figure. .
次に、８００℃で３０分ＮＨ３雰囲気中で加熱してゲー
ト電極の表面（上面と側面）にい膜１４を成長させる（
第１図（ｂ））。Next, a thin film 14 is grown on the surface (top and side surfaces) of the gate electrode by heating at 800° C. for 30 minutes in an NH3 atmosphere.
Figure 1(b)).
次いで第１図（Ｃ）に示される段階ではＳｉ基板１１を
０２雰囲気、８００℃で３０分熱処理して２００人の膜
厚の５ｉ０２膜１５を成長させると、ゲート電極の表面
は−０３膜１３ａで覆われ、しかも−０３は均一に形成
され、剥離しないことが確認された。Next, in the step shown in FIG. 1(C), the Si substrate 11 is heat-treated at 800° C. for 30 minutes in an O2 atmosphere to grow a 5i02 film 15 with a thickness of 200, and the surface of the gate electrode becomes a -03 film 13a. It was confirmed that -03 was covered with a uniform coating and did not peel off.
次いで９００℃水素処理を行うと、ＷＯ３はＷに還元す
る。このときＳｉＯ２は安定であるために、Ｗを用いた
安定なプロセスが可能になる。Then, when hydrogen treatment is performed at 900° C., WO3 is reduced to W. At this time, since SiO2 is stable, a stable process using W becomes possible.
しかる後に、砒素（Ａｓ”）のイオン注入を行って拡散
層１６（ソース、ドレイン領域）を形成し、ｒ’ｓＧ膜
１７を成長し、ＰＳＧ膜１７を窓開きして基板とのコン
タクト部１８、ゲート電極とのコンタクト部１９でそれ
ぞれ基板表面とゲート電極１３のタングステンを露出し
、ＡＪ電極配線１９を形成してＭＯＳトランジスタを完
成する。After that, arsenic (As'') ions are implanted to form a diffusion layer 16 (source and drain regions), an r'sG film 17 is grown, and a window is opened in the PSG film 17 to form a contact portion 18 with the substrate. , the substrate surface and the tungsten of the gate electrode 13 are exposed at the contact portion 19 with the gate electrode, and the AJ electrode wiring 19 is formed to complete the MOS transistor.
なお、上記の例はＷでゲート電極を形成する場合のもの
であるが、ＷのはかＭｏも使用可能であり、同じ工程で
形成されうるちのである。Note that, although the above example is for forming the gate electrode with W, it is also possible to use Mo instead of W, and the gate electrode can be formed in the same process.
本発明の第２実施例では、電極になるＷまたはＭｏの上
に、ＳｉＯ２もしくは窒化シリコン（Ｓｉ７Ｎｕ ）の
ような絶縁膜、またはＴｉＮのようなＷ ＋ Ｍｏと反
応しない導電膜を堆積し、このようにゲート電極の上に
被覆した膜をマスクにしてＷ、ＭＯをエツチングし、し
かる後にＮＨ３雰囲気中で熱処理を行いゲート電極の側
面の部分のＷもしくはＭｏを窒化することにより、その
後の熱処理におけるＷ、Ｍｏの剥離を防止する。In the second embodiment of the present invention, an insulating film such as SiO2 or silicon nitride (Si7Nu), or a conductive film such as TiN that does not react with W+Mo is deposited on W or Mo, which becomes an electrode. In this way, W and MO are etched using the film coated on the gate electrode as a mask, and then heat treatment is performed in an NH3 atmosphere to nitride the W or Mo on the side surfaces of the gate electrode. Prevents peeling of W and Mo.
第２図を参照して本発明第２実施例について説明すると
、ＭＯＳ型半導体素子のゲート絶縁膜１２成長までは第
１実施例の場合と同様である。続いてゲート電極用のＷ
をスパンタ法により２０００人の厚さに堆積した後に、
ＳｉＨｇとＮＨ３とを用いた化学気相成長（ＣＶＤ ）
法により８００℃で窒化シリコンを１０００人の膜厚に
堆積して窒化シリコン膜２２を作る。レジスト２３をマ
スクにし、エツチングガスにＳＦ６を用いるリアクティ
ブ・イオン・エツチングで窒化シリコン膜とＷとを連続
してエツチングし、上に窒化シリコン膜２２がかぶさっ
たゲート電極１３を形成する。The second embodiment of the present invention will be described with reference to FIG. 2. The steps up to the growth of the gate insulating film 12 of the MOS type semiconductor device are the same as in the first embodiment. Next, W for the gate electrode.
After depositing it to a thickness of 2000 mm using the Spanta method,
Chemical vapor deposition (CVD) using SiHg and NH3
A silicon nitride film 22 is formed by depositing silicon nitride to a thickness of 1000 nm at 800° C. using a method. Using the resist 23 as a mask, the silicon nitride film and W are successively etched by reactive ion etching using SF6 as an etching gas, thereby forming the gate electrode 13 on which the silicon nitride film 22 is covered.
次に、８００℃、３０分、ＮＨ３雰囲気中で加熱してゲ
ート電極１３の両側壁にＷＮＩＩ！ｉ！１４を成長させ
る（第２図（ｂ））。Next, it is heated at 800° C. for 30 minutes in an NH3 atmosphere to form WNII! on both side walls of the gate electrode 13. i! 14 (Fig. 2(b)).
次いで、シリコン基板を９００℃で熱酸化し、２００人
の厚さの５ｉ０２膜１５を成長させる（第２図（Ｃ））
。Next, the silicon substrate is thermally oxidized at 900° C. to grow a 5i02 film 15 with a thickness of 200 μm (FIG. 2(C)).
.
以下、第１実施例の場合と同様に、９００℃水素処理、
Ａｓのイオン注入を行って拡散層１６（ソース。Hereinafter, as in the case of the first example, 900°C hydrogen treatment,
As ion implantation is performed to form the diffusion layer 16 (source).
ドレイン領域）を作り、−０３をＷに還元し、第２図＋
ｄ）に示されるＭＯＳ ）ランジスタを完成する。drain region) and reduce -03 to W, Figure 2+
Complete the MOS transistor shown in d).
第１実施例と第２実施例とを比較すると、第１実施例で
は、Ｒ，１，Ｅ、でゲート電極を形成するとき第１図（
ａ）に誇張して示したように電極のサイドエツチングが
若干発生し、レジスト２１の下にひさしが作られたよう
になり、レジストのパターンどおり真直ぐにエツチング
されず、またレジスト中のアルカリ金属汚染が発生する
のに対し、第２実施例では、レジストの直下にＳｉ３Ｎ
＋１膜が存在するため、サイドエツチングなしにレジス
ト２３のパターンどおりの異方性エツチングがなされ、
レジスト中のアルカリ金属汚染が防止され、加えてイオ
ン注入に対するマスク性が優れる利点がある。しかし、
Ｗの剥離防止の効果は再実施例とも同じである。Comparing the first embodiment and the second embodiment, in the first embodiment, when forming the gate electrode with R,1,E, as shown in FIG.
As shown exaggeratedly in a), some side etching of the electrode occurs, and an eaves are created under the resist 21, and the etching is not straight according to the resist pattern, and there is also alkali metal contamination in the resist. However, in the second embodiment, Si3N is formed directly under the resist.
Since the +1 film is present, anisotropic etching is performed according to the pattern of resist 23 without side etching.
This method has the advantage that alkali metal contamination in the resist is prevented and, in addition, has excellent masking properties for ion implantation. but,
The effect of preventing peeling of W is the same as in the second example.
上述した如く、Ｗゲート電極形成工程においてゲート電
極上部に窒化シリコンなどの膜を形成して耐酸化性をも
たせ、またソース、ドレイン用のイオン注入のマスクと
するとともに、側壁を窒化することにより、多結晶シリ
コンゲートと同様の安定したプロセスが可能になった。As mentioned above, in the step of forming the W gate electrode, a film of silicon nitride or the like is formed on the top of the gate electrode to provide oxidation resistance, and also to serve as a mask for ion implantation for the source and drain, and by nitriding the sidewalls. A stable process similar to that used for polycrystalline silicon gates has become possible.
なお、本発明は上記の例の場合に限定されるものでなく
、窒化シリコン膜に代えて５ｉＯｚ ＋ ＴｉＮも使用
可能であり、ゲート電極はＭｏで作る場合にも及ぶもの
である。Note that the present invention is not limited to the case of the above example, and it is also possible to use 5iOz + TiN instead of the silicon nitride film, and it also extends to the case where the gate electrode is made of Mo.
なお、Ｗ、Ｍｏ薄膜の窒化は公知の技術であるが（アメ
リカ特許第４４７１００４号）、その場合には窒化後に
水素処理によってＷ、Ｍｏに変換してから使用するもの
であるので、ＷやＭｏの窒化物をそのまま残して酸化防
止に使う点において、上記した技術は新規なものと解す
る。Note that nitriding of W and Mo thin films is a known technique (US Pat. No. 4,471,004), but in that case, after nitriding, it is converted to W and Mo by hydrogen treatment before use. The above-mentioned technology is considered to be new in that the nitride is left intact and used for oxidation prevention.
以上述べてきたように本発明によれば、ＭＯ５型半導体
装置の製造において、Ｗ、Ｍｏなどの如き低抵抗率の高
融点金属でゲート電極を形成しても、それは後工程の熱
処理において剥離することがないものであり、半導体集
積回路の高集積化に有効である。As described above, according to the present invention, in the manufacture of MO5 type semiconductor devices, even if the gate electrode is formed of a high melting point metal with low resistivity such as W or Mo, it will peel off during the heat treatment in the post-process. This is effective for increasing the degree of integration of semiconductor integrated circuits.
第１図ｔａ＋〜ｆｄ）は本発明第１実施例断面図、第２
図（ａｌ〜（ｄｉは本発明第２実施例断面図、第３図は
従来例断面図である。
第１図と第２図において、
１１はＳｉ基板、
１２はゲート絶縁膜、
１３はゲート電極、
１４は−Ｎ膜、
１５は ５ｉＯｚ膜、
１６は拡散層、
１７はＰＳＧ膜、
１８は基板とのコンタクト部、
１９はゲート電極とのコンタクト部、
２２は窒化シリコン膜、
２１と２３はレジストである。
代理人 弁理士 久木元 彰
復代理人 弁理士 大 菅 義 之
ヘ
一〜
Δ
□□
ＯＤ
ψ□
へ ■
【Fig. 1 (ta+ to fd) is a sectional view of the first embodiment of the present invention;
Figures (al to (di) are cross-sectional views of the second embodiment of the present invention, and Figure 3 is cross-sectional views of the conventional example. In Figures 1 and 2, 11 is a Si substrate, 12 is a gate insulating film, and 13 is a gate Electrodes, 14 is a -N film, 15 is a 5iOz film, 16 is a diffusion layer, 17 is a PSG film, 18 is a contact part with the substrate, 19 is a contact part with the gate electrode, 22 is a silicon nitride film, 21 and 23 are It is a resist. Agent: Patent attorney: Gen Kuki; Agent: Yoshiyuki Osuga, patent attorney: Heichi~ Δ □□ OD ψ□ To ■ [
Claims (2)
（１１）上に前記金属で作った電極（１３）の上面およ
び側面に窒化物（１４）を形成し、 酸素雰囲気中の熱処理によって前記窒化物（１４）を酸
化物（１３ａ）とし、かつ、半導体基板（１１）の表面
に酸化膜（１５）を形成し、 次いで水素雰囲気中の熱処理によって前記酸化物（１３
ａ）を還元することを特徴とする半導体装置の製造方法
。(1) In the manufacture of semiconductor devices using high-melting point metals, nitrides (14) are formed on the top and side surfaces of electrodes (13) made of the metals on the semiconductor substrate (11) by nitriding in an ammonia (NH_3) atmosphere. , convert the nitride (14) into an oxide (13a) by heat treatment in an oxygen atmosphere, and form an oxide film (15) on the surface of the semiconductor substrate (11), and then heat treatment in a hydrogen atmosphere to form an oxide film (15). The oxide (13
A method for manufacturing a semiconductor device, comprising reducing a).
ておき、しかる後に該電極の側壁に窒化物（１４）を形
成する特許請求の範囲第１項記載の方法。(2) The method according to claim 1, wherein a nitride (22) is formed on the upper surface of the electrode (13), and then a nitride (14) is formed on the side wall of the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13146087A JPS63299273A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13146087A JPS63299273A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63299273A true JPS63299273A (en) | 1988-12-06 |
Family
ID=15058478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13146087A Pending JPS63299273A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63299273A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100441999B1 (en) * | 2002-08-23 | 2004-07-30 | 삼성전자주식회사 | Method for forming an electric layer and an electric pattern in semiconductor device |
-
1987
- 1987-05-29 JP JP13146087A patent/JPS63299273A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100441999B1 (en) * | 2002-08-23 | 2004-07-30 | 삼성전자주식회사 | Method for forming an electric layer and an electric pattern in semiconductor device |
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