JPS6181327U - - Google Patents
Info
- Publication number
- JPS6181327U JPS6181327U JP16547484U JP16547484U JPS6181327U JP S6181327 U JPS6181327 U JP S6181327U JP 16547484 U JP16547484 U JP 16547484U JP 16547484 U JP16547484 U JP 16547484U JP S6181327 U JPS6181327 U JP S6181327U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- output
- signal
- circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 1
Description
第１図は本考案によるマイクロコンピユータの
オートリセツト回路の一実施例を示す回路図、第
２図は本考案によるマイクロコンピユータのオー
トリセツト回路の他の実施例を示す回路図である
。
１，１０…マイクロコンピユータ、２，３…入
力キースイツチ、４…インバータ、１１…入力キ
ーマトリクス、１１ａ〜１１ｈ…入力キースイツ
チ、１２，１３…トランジスタ。
FIG. 1 is a circuit diagram showing one embodiment of the auto-reset circuit for a microcomputer according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the auto-reset circuit for a microcomputer according to the present invention. DESCRIPTION OF SYMBOLS 1, 10... Microcomputer, 2, 3... Input key switch, 4... Inverter, 11... Input key matrix, 11a-11h... Input key switch, 12, 13... Transistor.
Claims (1)
入力ポートの選択使用によつて使い分けを行なう
回路に於いて、前記マイクロコンピユータの不使
用入力ポートに対応して出力が発生される現在不
使用中の出力ポートから発生される出力信号を検
出し、この検出信号により前記マイクロコンピユ
ータにリセツト処理を加えることによつて、誤入
力信号に対する誤制御を防止することを特徴とす
るマイクロコンピユータのオートリセツト回路。 In a circuit that uses commonly-specified microcomputers by selectively using their input ports, an output is generated corresponding to an unused input port of the microcomputer from a currently unused output port. 1. An auto-reset circuit for a microcomputer, characterized in that it detects a generated output signal and applies reset processing to the microcomputer based on this detection signal, thereby preventing erroneous control in response to an erroneous input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16547484U JPS6181327U (en) | 1984-10-31 | 1984-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16547484U JPS6181327U (en) | 1984-10-31 | 1984-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181327U true JPS6181327U (en) | 1986-05-30 |
Family
ID=30723323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16547484U Pending JPS6181327U (en) | 1984-10-31 | 1984-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181327U (en) |
-
1984
- 1984-10-31 JP JP16547484U patent/JPS6181327U/ja active Pending
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