JPH0312113U - - Google Patents

Info

Publication number
JPH0312113U
JPH0312113U JP7186089U JP7186089U JPH0312113U JP H0312113 U JPH0312113 U JP H0312113U JP 7186089 U JP7186089 U JP 7186089U JP 7186089 U JP7186089 U JP 7186089U JP H0312113 U JPH0312113 U JP H0312113U
Authority
JP
Japan
Prior art keywords
processing section
signal processing
interface circuit
gain
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7186089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7186089U priority Critical patent/JPH0312113U/ja
Publication of JPH0312113U publication Critical patent/JPH0312113U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案に係るインターフエイス回路
の一実施例を示す回路図、第2図は従来のインタ
ーフエイス回路を含む回転数測定回路を示す回路
図である。 2…回転センサ、7…スイツチ素子、8…信号
処理部、9…不揮発性メモリ。
FIG. 1 is a circuit diagram showing an embodiment of an interface circuit according to this invention, and FIG. 2 is a circuit diagram showing a rotation speed measuring circuit including a conventional interface circuit. 2... Rotation sensor, 7... Switch element, 8... Signal processing unit, 9... Non-volatile memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] センサ2からの検出信号の信号処理を信号処理
部で施して出力するインターフエイス回路におい
て、上記信号処理部8のゲインを切換えるための
スイツチ素子7と、このスイツチ素子を設定され
た記憶データに基づいてオンまたはオフせしめる
不揮発性メモリ9とを備えたことを特徴とするイ
ンターフエイス回路。
In the interface circuit that processes the detection signal from the sensor 2 in a signal processing section and outputs the signal, there is a switch element 7 for switching the gain of the signal processing section 8, and a switch element 7 for switching the gain of the signal processing section 8. 1. An interface circuit comprising: a non-volatile memory 9 that can be turned on or off by a switch.
JP7186089U 1989-06-20 1989-06-20 Pending JPH0312113U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7186089U JPH0312113U (en) 1989-06-20 1989-06-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7186089U JPH0312113U (en) 1989-06-20 1989-06-20

Publications (1)

Publication Number Publication Date
JPH0312113U true JPH0312113U (en) 1991-02-07

Family

ID=31609272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7186089U Pending JPH0312113U (en) 1989-06-20 1989-06-20

Country Status (1)

Country Link
JP (1) JPH0312113U (en)

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