JPS6180699A - Mos transistor output circuit - Google Patents

Abstract

PURPOSE:To generate an output high level to driven directly a CMOS load and to obtain an output circuit which is not much affected by the fluctuation of a manufacturing process attaining a reduction of access time by installing a pull-up transistor and a pull-up driving circuit. CONSTITUTION:When I/O is the high level and I/O is the low level, a nodal point N1 becomes the high level and a nodal point N2 becomes the low level, and therefore, an output terminal OUT will not change while a Vcc level is kept. Reversely, when an input I/O is the low and I/O is the high level, the nodal point N1 preserves the low level and N2 is changed to the high level. The high level of an output terminal OUT is reset by a transistor Q2 and simultaneously, the gate electric potential of a pull-up transistor Q30 is reset to the low level by conducting a transistor Q34 with the high of the nodal point N2. Consequently, the time until the output terminal OUT becomes the low level is an access time, and the maximum value of the low level of a normal input for a CMOS load is 1.35 V (electric power source voltage 4.5VX0.3), and therefore, a quick access time can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an output circuit using MO8 transistors.

[Purpose of the invention]

Generally, when supplying the output of a circuit to an external circuit, if the interface is different or the supply means (connection line, etc.) has a heavy load, it is often necessary to provide an output circuit to function as a buffer between the two. When the circuit is an integrated circuit, the output circuit is also formed of the same semiconductor element as the circuit, such as a MOS transistor, and is incorporated into the same integrated circuit.

An example of a conventional MOS transistor output circuit of this type is shown in FIG. In this example, a flip-flop FF activated by an activation signal φ1 at the same level as the power supply voltage Vcc is connected in cascade between the power supply voltage Vcc and the ground potential, and the output of the flip-flop F'F is connected from the connection point OUT. Two MOs with output node Nl or N2 of flip 70-tube FF connected to their respective gates for external supply
8) The input I10. of the flip-flop FF in the output circuit 4-3, for example, as shown in FIG. For example, Ilo is as shown in Figure 2? 5
1'i4"RA configured in a matrix of 6 rows x 256 columns
It is connected to the Ilo pass line 42 of M41, and carries the read code from the □ memory cell.

Since the configuration of flip-flop FF itself and the circuit for generating activation signal φ1 shown in FIG. 3 are well known, detailed explanation thereof will be omitted here. FIG. 4 shows a time chart for explaining the operation of the conventional example. The signal φ is initially at a low level (signal φ is at a high level), and transitions to a high level after receiving successive signals from the memory cell. Activation signal φ1 is set to high level (power supply voltage VCC
(equivalent to ).

Now, if input I10 is at high level and Ilo is at low level, node N is reached by the output of flip 70-tube FF.
1 and N2 are settled as high level and low level, respectively. Therefore, the transistor Ql becomes conductive, the transistor Q2 becomes non-conductive, and the potential of the output OUT becomes the node N
From the power supply voltage Vcc at the level of 1, the transistor Q1
The value obtained by subtracting the threshold voltage VtHt is obtained. This value is when there is no current load on the output OUT,
Fluctuations in power supply voltage Vcc and current load (HMAx=5
mA), the output voltage is Z4'i (standard value).

In such a conventional configuration, the source of the gate voltage of the transistor Ql is only the activation signal φl at the same level as the power supply voltage Vcc, so the potential at the node N1- can only rise to the power supply voltage Vccf at most. First, as mentioned above, the potential of the output OUT can only be guaranteed to be 24cm, and there is a problem that the level is insufficient to supply this to the external circuit and it may not be possible to match the interface. For example, due to its low power consumption, it has made remarkable progress in recent years.
The minimum input voltage value (CVxaMxn) of CMOB, whose field of use has now expanded to rival TTL, is 70% of the power supply voltage Vcc, and when the power supply voltage Vcc is 4.5V, "t' 41 V114MIN=3. 15vt-request i rate; b. Also, in the conventional configuration as described above,
Since the potential of the output OUT depends on the threshold voltage vTEH of the transistor Qr, it also has the disadvantage that it is easily influenced by variations in the manufacturing process.

Furthermore, VtsMn+=3. In the case of 15V, even if the output potential can be achieved, there is a drawback that the access time is delayed compared to the case of normal TTI and load.

(Object of the Invention) An object of the present invention is to provide a MOS transistor output circuit that generates a high output level that can be directly driven to an 0MO8 load, has a faster access time, and is resistant to manufacturing process variations. It is in.

(Structure of the Invention) The MOS transistor output circuit of the present invention is connected in cascade, both ends are held at a power supply potential and a ground potential, and the level of the power supply potential and the level of the ground potential are switched from the connection point and output to the outside. an output circuit that drives the first and second MOS transistors, and the first and second MOS transistors connected in parallel with the N1 MOS transistor between the connection point and the power supply potential; The output circuit includes a pull-up transistor, and a drive circuit that raises the gate potential of the pull-up transistor to a potential higher than the power supply simultaneously with, or prior to, activation of the output circuit. - (Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 5 shows a circuit diagram of an embodiment of the present invention, and FIG. 6 shows its operating waveforms. This embodiment is a flip-flop FP.
and an output transistor Ql whose output is used as a gate signal.
, Q2. With a potential higher than VCC at the gate input, the power supply V
The pull-up transistor Q301 is connected between the output Vcc and the output 0L) and the pull-up drive circuit B1 generates a potential higher than the Vcc. The pull-up drive circuit Bl includes transistors Q3. Q4. Source is transistor Q
A transistor Q5. whose gate is connected to the power supply Vcc at the connection point of L Q4. The capacitor C30 is connected in cascade between the signal φ and the ground potential, and each gate is connected to the node of the transistor Qs and the gate of the pull-up transistor Q3G.

The pull-up drive circuit B1 starts operating upon the rise of the activation signal φ of the output circuit. Due to the rise of signal φ, node N3
is charged to the high level of the signal φ (Vcc potential). Signal φ1 rises after a certain delay time from the rise of signal φ, transistor Q6 becomes non-conductive, and node N3
Raise the voltage above Vcc. Therefore, at this point, the output terminal OUT is further charged to the power supply potential by the transistor Q30.

The output buffer is activated by the signal φl, so after the output terminal OUT is charged to the power supply potential Vcc, the node N1
and changes in N2 occur. Now I10 is high level, I
When lo is low level, node Nl is high level, node N
2 becomes low level, the output terminal OUT remains at the Vcc level and does not change.

In other words, the access time determined by the minimum value VOHMIN of the output high level is not a problem because a sufficiently high potential is applied to the output terminal OUT before the read data is amplified. Conversely, if input I10 is low level and Ilo is high level, node N1 remains low level and N! changes to a high level. The high level of the output terminal OUT is transferred to the transistor Q2.
At the same time as resetting the pull-up transistor Q◎
At the high level of the gate potential of all nodes Nz, the transistor Q3
4 is reset to low level by making it conductive. Therefore, the access time is until the output terminal OUT becomes low level, and the maximum value of the normal input low level in the case of 0MO8 load is 1.35v (power supply voltage 4.5v x 0.3)
Therefore, a fast access time can be obtained.

As described above, in this embodiment, the output terminal is charged to the power supply potential using the pull-up transistor prior to activation of the output buffer. Thereafter, the level of the output terminal is determined by the output of the output buffer, and the potential of the output terminal is determined while controlling the above-mentioned pull-up transistor in response to the output result. Even if the output terminal remains at a high level for a short period of time after the start of operation, the circuit that receives the output signal from this output terminal will
Normally, there is some delay time until the output signal is determined, so there is no problem in actual use.

(Effects of the Invention) As explained above, the present invention provides the following effects by providing a pull-up transistor and a pull-up drive circuit.

(1) Since the output high level reaches the power supply potential, direct connection with CMOS devices is possible.

(2) Since the 7" access time is determined on the low level side, it is possible to increase the speed.

(3) Driving ability for TTL load is transistor Q1
By appropriately selecting the abilities of Q2 and Q2, both can be satisfied.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of a conventional MOS transistor output circuit and a block diagram connected to this output circuit 'i64kRAM41.
1, the circuit diagram of the generation circuit, Fig. 4 is the MOS shown in Fig. 1.
FIGS. 5 and 6 are charts showing operating waveforms of the transistor output circuit. FIGS. 5 and 6 are a circuit diagram of an embodiment of the present invention and charts showing its operating waveforms. 41-...64kRAM, Bl...pull-up, destination circuit, FF...flip-flop,
OUT , , , , Output, Q30...Pull-up transistor, φ, i. φl --- Activation signal. Agent Patent Attorney Uchihara “−゛ゝ日、＋−１゛gu−

Claims (1)

[Claims] first and second first and second circuits connected in cascade, both ends of which are held at a power supply potential and a ground potential, and which switch the level of the power supply potential and the level of the ground potential from the connection point and output the same to the outside;
a MOS transistor, an output circuit that drives the first and second MOS transistors, a pull-up transistor connected in parallel with the first MOS transistor between the connection point and the power supply potential, and the pull-up transistor. 1. A MOS transistor output circuit comprising: a drive circuit which sets the gate potential of the transistor to a potential higher than a power supply simultaneously with or prior to activation of the output circuit.