JPS6180596A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To detect and amplify without converting an electric current difference to an electric potential difference by a resistance by connecting 10 MISFETs including a load element prescribedly and forming a circuit. CONSTITUTION:A sense amplifier circuit is formed by 10 pieces of MISFET of depletion type MISFET 1, 3, 5 and 7 and MISFET 2, 4, 6, 8, 9, 10, 11 and 12. For example, when the electric current of an input terminal 13 is larger than an input terminal 14, in a connecting point 24, its electric potential is changed quickly compared with a connecting point 25, FET 2 is off and the electric potential of the output terminal 15 becomes the electric potential VDD of an electric power source 20. Thus, FET 6 is on, the electric potential of a connecting point 22 becomes the electric potential VSSs of a power source 21, FET 10 is off, the electric potential of a connecting point 25 will not be changed FET 4 is kept to be on. As this result, the fact that the electric potential of the connecting point 16 becomes the electric potential VSS, and the electric current of the terminal 13 is large, is detected without converting to electric current difference and electric potential difference by a resistance and influencing dispersion of a resistance value, and this can be amplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit suitable for a memory circuit configured with MISFETs.

[Prior art]

In recent years, as the capacity of dynamic memory circuits using MISFETs has increased, there has been active development of memory cells that can be realized in a small area. Some such memory cells distinguish between two states corresponding to two logic levels by differences in the current flowing through the memory cell when read.

However, in the conventional MI 5FET integrated circuit, there was no known circuit that could effectively detect the difference in current. Therefore, in the past, a resistor was used to convert the current into voltage and detect the difference in potential. An amplifier was used to detect which of two states it was in (fEEE Trtns, on El
ectron Devlees vol, ED-29 (
1982) 707-714)). If the current difference between the two states in this case is ΔW, and the resistance through which the current flows is R, then the following relationship holds true between the resulting potential difference ΔV, ΔI, and R according to Ohm's law.

ΔV=RX ΔI Therefore, in order to obtain a large potential difference, the resistance value R must be increased.

[Problem that the invention seeks to solve]

However, in MXS integrated circuits, it is difficult to manufacture resistors with high precision, especially those with large resistances. Therefore, when the detection circuit is constructed using an MIS integrated circuit, there is a risk that it will not operate properly due to variations in resistance values.

In view of this point, it is an object of the present invention to provide a sense amplifier circuit particularly suitable for detecting differences in current.

Rounding Means for Solving Problem c] The present invention provides a first load element (MISFET) with one end connected to the first power supply 20 and the other end connected to the first output terminal 15.
1, and a first MIS whose drain electrode is connected to the first output terminal 15 and whose source electrode is connected to the second power supply 21.
FET 2 and a second load element (MIS) whose one end is connected to the first power supply 20 and the other end is connected to the second output terminal 16.
FET) 3 and the drain direct product to the second output terminal 1.
a second MISFET 4 whose source electrode is connected to the second power source 21 and whose one end is connected to the first power source 20;
a third load element (MzspEr) 5 whose other end is connected to the first connection point 22 and whose drain electrode is connected to the first connection point 22;
Connect to connection point 22 of ? -) a third MISFET 6 whose electrode is connected to the first output terminal 15 and whose source electrode is connected to the second power supply 21; one end is connected to the first power supply 20 and the other end is connected to the second A fourth load element (MISFET) 7 is connected to the connection point 23 of A fourth MISFET 8 is connected to the second power supply 21, and its drain electrode is connected to the gate electrode 1 of the first MISFET 2. -) a fifth MlsFET 9 whose electrode is connected to the second connection point 23 and whose source electrode is connected to the first input terminal 13; and a sixth M whose gate electrode is connected to the first connection point 22 and whose source electrode is connected to the second input terminal 14.
ISFET 10 and the drain electrode connected to the first power supply 2
0, the gate electrode is connected to the clock input terminal 19, and the source electrode is connected to the first) MISFET 2 nor -.
to'! a seventh OMISFET 11 connected to the terminal, a drain electrode connected to the first power supply 2o, a gate electrode connected to the clock input terminal 19, and a source electrode connected to the second
The eighth MI connected to the gate electrode of MISFET 4
This is a sense amplifier circuit characterized by comprising an SFET 12.

〔Example〕

Hereinafter, one concrete example of the present invention will be explained according to the g1 diagram. In the following embodiments, an MQ 5FET will be explained, but it goes without saying that the present invention can be applied to MISFETs in general.

In Figure 1, a 7" Gressi, l/type MOSFET
1.3, 5, and 7 operate as two-terminal load elements.

MOSFET 1, 31': j-t's MOSFET
Both ET 2 and ET 4 constitute an inverter. M.O.
SFETs 1 and 3 and MOSFETs 2 and 4 are matched in electrical characteristics.

MOSFET 1 is connected to the clock input terminal 19 during standby.
A potential at rt is applied that causes 4 passes through MO8FETs 2 and 12, and as a result, the potential at the connection points 24 and 25, where the gate electrodes of MO8FETs 2 and 4 are connected, is at the d level vD of the power supply 20.
D is approximately equal to D, and MOSFETs 2 and 4 are both conductive. Therefore, a potential approximately equal to the potential Vllll of the power supply 21 is applied to both the output terminals 15 and 16.

During operation, MOSFET 11 is connected to clock input terminal 19.
and 12 are applied. Input terminals 13 and 1
Currents to be compared are applied to 4, and these currents discharge the stray capacitance 17 of the connection point 24 and the stray capacitance 18 of the connection point 25, respectively. As a result, connection points 24 and 25
The potential of the power source 21 changes in the same manner as the potential VaS of the power supply 21. Here, it is assumed that the values of stray capacitances 16 and 17 are equal. In general, in MO8FET integrated circuits, the capacitance value is largely determined by the geometrical shape and is therefore much easier to control than the resistance value. Therefore, this condition can be easily met.

Now, suppose that the current applied to the input terminal 13 is larger than the current applied to the input terminal 14. In this case, the potential at the connection point 24 changes faster than the potential at the connection point 25. As a result, the MOSFET 2 is eventually cut off, and the potential of the output terminal 15 becomes ``1'' DD of the power supply 20. This makes p MOSFET 6 conductive and connection point 22
When the potential of p is approximately equal to the potential Mil11 of the power supply 21,
MOSFET 10 is shut off. As a result, the potential at the connection point 25 does not change, the MOSFET 4 remains conductive, and the potential at the output terminal 16 is maintained at a potential close to V++sK. In this way, the potential at the connection point 15 becomes VD
When the potential at the D% connection point 16 is close to '/ag, it can be detected that the current being applied to the input leakage element 13 is larger.

In the circuit of FIG. 1, the potential of the output terminal 15 is set to VDD, the potential of the connection point 22 is set to a potential close to VB2, and the MOS
Even after FET 10 is shut off, if the leakage current of MOSFET 10 is large, the capacitance 18 is released little by little, and after a sufficient period of time, MOSFET 4 becomes a
ll'r, and the potential of the output terminal 16 becomes the output terminal 1.
It is conceivable that the potential becomes vDD, which is equal to the potential of No. 5.

FIG. 2 shows the configuration of a circuit that operates even when the leakage current is large. The circuit in Figure 2 is the MO of the circuit in Figure 1.
MOSFETs in parallel with SFETs 11 and 12, respectively.
31 and 32 have been added. As in the circuit of FIG. 1, it is assumed that the current applied to the input terminal 13 is larger than the current applied to the input terminal 14 by υ.

In the standby state, the potential of output terminals 15 and 16 is VSS.
Since it is approximately equal to , both MOSFETs 31 and 32 are cut off. MOSFETs 11 and 12 are cut off to put the circuit into operation, and when the potential of MOSFET 2's i@L output terminal 15 reaches VDD, MOSFET
At the same time MOSFET 10 is turned off, MOSFET 32 becomes conductive. As a result, the potential at the connection point 25 is raised to VDD and remains at this value thereafter. Therefore, regardless of the presence or absence of leakage current in MOSFET 10, MOSFET 4 is maintained in a conductive state.

In each of the above embodiments, the stray capacitance was considered as the capacitance i17.18, but a separate capacitive element may be added as required. Also, as the circuit that actually generates the output, a simple inverter circuit consisting of MOSFETs 1 and 2 and MOSFETs 3 and 4 is used, but this is fine)
In some cases, better characteristics can be obtained by using a high-gain cascode amplifier circuit or Schmitt trigger circuit.

〔Effect of the invention〕

As described above, according to the present invention, a current difference can be detected without changing to a potential difference through a resistor.

Since it is possible to obtain a current value detection type sense amplifier circuit that can perform amplification and is not affected by variations in resistance values, it is highly effective in MIS memory using current detection type memory cells.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing embodiments of the present invention. 1.2.3, 4, 5, 6, 7, 8.9, 10, 11, 1
2.31゜32...MOSFET, 13, 14.
...Input terminal. 15, 16...output terminals. 17.1
8...Capacity. 19...Clock input terminal. 20, 21... Denryo G

Claims (1)

[Claims] (1) A first load element having one end connected to a first power supply and the other end connected to a first output terminal, and a drain electrode connected to the first
a first MISFET connected to the output terminal of the first MISFET and having its source electrode connected to a second power supply; a second load element having one end connected to the first power supply and the other end connected to a second output terminal; a second MISFET having a drain electrode connected to the second output terminal and a source electrode connected to the second power source; one end connected to the first power source and the other end connected to the first connection point; a third load element, a third MISFE having a drain electrode connected to the first connection point, a gate electrode connected to the first output terminal, and a source electrode connected to the second power source;
a fourth load element having one end connected to the first power supply and the other end connected to the second connection point; a fourth load element having a drain electrode connected to the second connection point and a gate electrode connected to the second connection point; a fourth M connected to the output terminal and having its source electrode connected to the second power source;
ISFET, and the drain electrode is connected to the first MISFET.
a fifth M, the gate electrode being connected to the second connection point and the source electrode being connected to the first input terminal;
ISFET, and the drain electrode is connected to the second MISFET.
a sixth M, the gate electrode being connected to the first connection point and the source electrode being connected to the second input terminal;
ISFET, and a seventh MISFET having a drain electrode connected to the first power source, a gate electrode connected to the clock input terminal, and a source electrode connected to the gate electrode of the first MISFET.
ISFET, an eighth MISFET having a drain electrode connected to the first power supply, a gate electrode connected to the clock input terminal, and a source electrode connected to the gate electrode of the second MISFET.
A sense amplifier circuit comprising: a MISFET.