JPS6178352U - - Google Patents
Info
- Publication number
- JPS6178352U JPS6178352U JP15983284U JP15983284U JPS6178352U JP S6178352 U JPS6178352 U JP S6178352U JP 15983284 U JP15983284 U JP 15983284U JP 15983284 U JP15983284 U JP 15983284U JP S6178352 U JPS6178352 U JP S6178352U
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- direct memory
- abnormal termination
- circuit
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000609 electron-beam lithography Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 1
Landscapes
- Bus Control (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15983284U JPS6178352U (el) | 1984-10-24 | 1984-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15983284U JPS6178352U (el) | 1984-10-24 | 1984-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6178352U true JPS6178352U (el) | 1986-05-26 |
Family
ID=30717778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15983284U Pending JPS6178352U (el) | 1984-10-24 | 1984-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6178352U (el) |
-
1984
- 1984-10-24 JP JP15983284U patent/JPS6178352U/ja active Pending
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