JPS617778A - Output signal processing circuit of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To eliminate surely fluctuation of a DC bias voltage over one picture element signal period and superimposition of a leakage signal of reset pulse by quantizing two portions, a flat portion and a picture signal portion during the one picture element period and subtracting a quantized output at each picture element. CONSTITUTION:An A/D converter 24 quantizes a flat part P as a reference signal period and a strobe pulse SDP fed to the converter 24 is generated nearly at the center of the flat part. An A/D converter 25 quantizes a picture signal and a strobe pulse SDi fed to the converter 25 is generated nearly at the center of the picture signal. Two kinds of signals comprising a reference signal and a picture element signal are obtained during one picture element by the converters 24, 25, and an output signal of the converters 24, 25 is stored respectively in storage section 26, 27. Data of the storage sections 26, 27 is read at each corresponding picture element, subtraction processing is executed sequentially by a substractor 28 and a picture signal eliminated with fluctuation is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention relates to an output signal processing circuit for a solid-state image sensor, such as a COD image sensor.

[Technical background of the invention and its problems]

FIG. 4 shows an output signal processing circuit of a conventional COD image analyzer. As shown in FIG. 5, the output signal of the COD image sensor 11 includes, in addition to the image signal vi, a DC bias (offset) voltage v0 and a reset pulse leakage signal vR8. DC bias voltage ■. and reset) /-t'
It is necessary to remove the pulse leakage signal vR8. That is, the output signal of the COD image basket/sustainer 11 is supplied to a sample and hold circuit 12, and in this circuit 12, a DC bias voltage V is extracted by a strobe pulse SH1. This extracted voltage ■ is applied to the p,/b converter 13,
After being converted into a complete DC voltage through a converter 14, the subtracter 1 is applied together with the output signal of the CCD image sensor 1.
5, and the DC bias voltage is removed from the output signal of the CCD image sensor 1. The output signal of this subtracter 15 is supplied to a sample hold circuit 16, and an image signal is extracted by a strobe pulse 5P12.

Therefore, an image signal from which the leakage signal of the reset pulse has been removed is output from the output signal of the Sansol hold circuit 16, and this signal is converted into a digital signal by the x/b converter 17 and then stored. The information is stored in the section 18. It should be noted that SDI + "'D2 is an o-b pulse for conversion.

By the way, in the sample and hold circuit 12, the DC bias voltage v is set at a period shorter than the sampling period.
0 fluctuates, the sample-and-hold circuit 12 cannot follow this fluctuation, so the output signal amplitude of the differential amplifier 15 increases or decreases by the fluctuation portion of the DC bias voltage V, and the DC bias voltage v0 is reliably removed. A problem arises that makes it difficult to

[Purpose of the invention]

This invention was made based on the above-mentioned circumstances, and its purpose is to ensure that even if the DC bias voltage fluctuates in one pixel signal period or more, even if the leakage signal of the reset pulse is superimposed. It is an object of the present invention to provide an output signal processing circuit for a solid-state image sensing device that can eliminate the problem.

[Summary of the invention]

This invention advances the pulse timing of a reset pulse that drives a CCD image sensor, provides a flat portion as a reference signal period in the output signal of the image sensor, and
The signal levels at two locations, the flat portion and the image signal portion, are extracted during one pixel period of the image sensor, and only the image signal is extracted by subtracting the two signal levels.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, shift pulses φ, clock pulses φ1, φ2, ah', and reset pulses φ, S are supplied from a Noculus generation circuit 22 to a solid-state imaging device, for example, a CCD image sensor 21. The waveforms of the clock pulses φl, φ2 and the reset pulse -R80 are shown in FIGS. 2(a), 2(b) and 2(c), respectively. Here, the high level period of reset pulse φR8 is as follows:
Clock pulse φl is located at the third timing from the front that divides the μ period A of φ2 into four, that is, the first timing from the trailing edge, and is advanced by 9 A/4 periods compared to the normal timing. .

In this way, the reset nozzle φ. By supplying the signal, a flat portion P as a reference signal period will always occur at one point in one pixel period in the signal transferred and output from the CCD image sensor 11, as shown in FIG. 2(d). The output signal of this CCD image sensor 21 is a DC bias voltage V. are supplied through capacitors 23 to wheat exchangers 24 and 25, respectively. Among these, the h/b converter 24 quantizes the flat part P as the reference signal period, and the strobe pulse SDP supplied to the A/D converter 24 is shown in FIG. 2(d). As shown, it is generated at approximately the center of this flat part P.
The strobe converter 25 quantizes the image signal (shown by the shaded area i in FIG. 2(d)), and the strobe pulse SDi supplied to this converter 25 is as shown in FIG. ), it is generated approximately at the center of this image signal.

Two types of signals consisting of a reference signal and an image signal are obtained within one pixel period by these A/i) converters 24 and 25, and the output signals of these A/b converters 24 and 25 are respectively stored in a storage section 26. .27. When the quantization of all pixel elements is completed in this way, the data stored in the storage units 26 and 27 is read out for each corresponding pixel, and the subtracter 28
is supplied to That is, this subtracter 28 first performs subtraction processing between the image signal of the first pixel and the reference signal, and then subtracts the image signal of the first pixel and the reference signal.
Subtraction processing is performed sequentially for the 1st pixel, 3rd pixel, etc., and an image signal from which fluctuations have been removed is output.

According to the above embodiment, the pulse timing of the reset pulse φR8 that drives the CCD image sensor 21 is phase-advanced to provide a flat portion P as a reference signal movement amount in the output signal of the image sensor 21, and this flat portion P is provided in the output signal of the image sensor 21 in one pixel period. Two parts, part P and image signal part 1, are quantized, and these quantized outputs are subtracted for each pixel. Therefore, since subtraction processing is performed for each pixel, the DC bias voltage
Even if the leakage signal of 4 pulses fluctuates in one pixel period or more, it is possible to reliably remove the leakage signal of the DC bias voltage and reset pulse.

In the above embodiment, two converters were used to separately quantize the flat part P and the image signal l, but 311 converters as shown in FIG. The pulse SDr' SPi may be supplied, and the quantized reference signal and image signal may be selectively stored in the storage sections 33 and J4 according to the chip select signal CS.

It goes without saying that other modifications can be made without departing from the gist of the invention.

〔Effect of the invention〕

As detailed above, according to the present invention, even if the DC bias voltage fluctuates in one pixel signal period or more, even if the leakage signal of the reset pulse is superimposed, it is possible to reliably remove these signals. An output signal processing circuit for an image sensor can be provided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an output signal processing circuit of a solid-state imaging system according to the present invention, FIG. 2 is a waveform diagram shown to explain the operation of FIG. 1, and FIG. 3 is a diagram showing the present invention. FIG. 4 is a block diagram showing an output signal processing circuit of a conventional solid-state image sensor, and FIG. 5 is a waveform diagram showing an output signal of a CCD image sensor. 21... CCD image sensor, 24, 25° 31.
...A/b converter, 26, 27, 33.34...Storage section, 28...Subtractor, φ, 8...Reset pulse. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1, Figure 2, Figure 3, Figure 4, Figure 51! T

Claims (3)

[Claims] (1) A solid-state image sensor that transfers an analog signal in accordance with a clock pulse, means for generating a reset pulse for the solid-state image sensor by advancing the phase from the trailing edge of the clock pulse, and a means for generating a reset pulse for the solid-state image sensor that is output from the solid-state image sensor. A solid-state imaging device characterized by comprising means for respectively quantizing a reference signal period and a photoelectric conversion period of input light within one pixel period of a signal, and means for subtracting the quantized signals of both periods. output signal processing circuit. (2) A patent characterized in that the quantizing means includes two A/D converters, and the signals of each period quantized by these A/D converters are stored in corresponding storage units. An output signal processing circuit for a solid-state image sensor according to claim 1. (3) The quantizing means includes one A/D converter, and the signals of each period quantized by the A/D converter are selectively stored in corresponding storage units. An output signal processing circuit for a solid-state image sensor according to claim 1.